STM8S007C8 datasheet(24/92 Pages) STMICROELECTRONICS

24 / 92 page

Pinouts and pin descriptions

STM8S007C8

24/92

DocID022171 Rev 5

PC6/SPI_MOSI

I/O X

HS O3

Port C6

SPI master

out/



slave in

PC7/SPI_MISO

I/O X

HS O3

Port C7

SPI master in/

slave out

PG0

I/O X

XO1

Port G0

PG1

I/O X

XO1

Port G1

PE3/TIM1_BKIN

I/O X

Port E3

Timer 1 -



break input

PE2/I2C_SDA

I/O X

XO1 T(2)

Port E2 I2C data

PE1/I2C_SCL

I/O X

XO1 T(2)

Port E1 I2C clock

PE0/CLK_CCO

I/O X

HS O3

Port E0

Configurable

clock output

PD0/TIM3_CH2

I/O X

HS O3

Port D0

Timer 3 -

channel 2

TIM1_BKIN

[AFR3]/

CLK_CCO

[AFR2]

PD1/SWIM(3)

I/O X

XHS O4

Port D1

SWIM data

interface

PD2/TIM3_CH1

I/O X

HS O3

Port D2

Timer 3 -

channel 1

TIM2_CH3

[AFR1]

PD3/TIM2_CH2

I/O X

HS O3

Port D3

Timer 2 -

channel 2

ADC_ETR

[AFR0]

PD4/TIM2_CH1/B

EEP

I/O X

HS O3

Port D4

Timer 2 -

channel 1

BEEP output

[AFR7]

PD5/ UART3_TX

I/O X

Port D5

UART3 data

transmit

PD6/

UART3_RX(1)

I/O X

Port D6

UART3 data

receive

PD7/TLI

I/O X

Port D7

Top level

interrupt

The default state of UART1_RX and UART3_RX pins is controlled by the ROM bootloader. These pins are

pulled up as part of the bootloader activation process and returned to the floating state before a return from

the bootloader.

In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer, weak pull-up, and protection

diode to VDD are not implemented).

The PD1 pin is in input pull-up during the reset phase and after the internal reset release.

Table 5. STM8S007C8 pin description (continued)

Pin name

Input

Output

Default

alternate

function

Alternate

function

after remap

[option bit]

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