STM8L151C4 datasheet(58/142 Pages) STMICROELECTRONICS

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Interrupt vector mapping

STM8L151x4/6, STM8L152x4/6

58/142

DocID15962 Rev 15

TIM2

TIM2 update/overflow/

trigger/break interrupt

Yes

0x00 8054

TIM2

TIM2 capture/

compare interrupt

Yes

0x00 8058

TIM3

TIM3 update/overflow/

trigger/break interrupt

Yes

0x00 805C

TIM3

TIM3 capture/

compare interrupt

Yes

0x00 8060

TIM1

Update /overflow/trigger/

COM

Yes

0x00 8064

TIM1

Capture/compare

Yes

0x00 8068

TIM4

TIM4 update/overflow/

trigger interrupt

Yes

0x00 806C

SPI1

SPI1 TX buffer empty/

RX buffer not empty/

error/wakeup interrupt

Yes

0x00 8070

USART1

USART1 transmit data

transmission complete

interrupt

Yes

0x00 8074

USART1

USART1 received data

ready/overrun error/

idle line detected/parity

error/global error interrupt

Yes

0x00 8078

I2C1

I2C1 interrupt(3)

Yes

0x00 807C

1. The Low power wait mode is entered when executing a WFE instruction in Low power run mode. In WFE mode, the

interrupt is served if it has been previously enabled. After processing the interrupt, the processor goes back to WFE mode.

When the interrupt is configured as a wakeup event, the CPU wakes up and resumes processing.

2. The interrupt from PVD is logically OR-ed with Port E and F interrupts. Register EXTI_CONF allows to select between Port

E and Port F interrupt (see External interrupt port select register (EXTI_CONF) in the RM0031).

3. The device is woken up from Halt or Active-halt mode only when the address received matches the interface address.

Table 11. Interrupt mapping (continued)

IRQ

No.

Source

block

Description

Wakeup

from Halt

mode

Wakeup

from

Active-halt

mode

Wakeup

from Wait

(WFI

mode)

Wakeup

from Wait

(WFE

mode)(1)

Vector

address

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