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ST72325AR7-Auto датащи(PDF) 112 Page - STMicroelectronics

номер детали ST72325AR7-Auto
подробное описание детали  SCI asynchronous serial interface
PDF  243 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
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ST72325AR7-Auto датащи(HTML) 112 Page - STMicroelectronics

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Doc ID 13770 Rev 3
13.3.6
One Pulse mode
One Pulse mode enables the generation of a pulse when an external event occurs. This
mode is selected via the OPM bit in the CR2 register.
The one pulse mode uses the Input Capture1 function and the Output Compare1 function.
Procedure
To use one pulse mode:
1.
Load the OC1R register with the value corresponding to the length of the pulse (using
the appropriate formula below according to the timer clock source used).
2.
Select the following in the CR1 register:
–
Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after the
pulse.
–
Using the OLVL2 bit, select the level to be applied to the OCMP1 pin during the
pulse.
–
Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the
ICAP1 pin must be configured as floating input).
3.
Select the following in the CR2 register:
–
Set the OC1E bit, the OCMP1 pin is then dedicated to the Output Compare 1
function.
–
Set the OPM bit.
–
Select the timer clock CC[1:0] (see Table 62: Timer clock selection).
Then, on a valid event on the ICAP1 pin, the counter is initialized to FFFCh and OLVL2 bit is
loaded on the OCMP1 pin, the ICF1 bit is set and the value FFFDh is loaded in the IC1R
register.
Figure 53.
One pulse mode cycle flowchart
Because the ICF1 bit is set when an active edge occurs, an interrupt can be generated if the
ICIE bit is set.
Clearing the input capture interrupt request (that is, clearing the ICFi bit) is done in two
steps:
1.
Reading the SR register while the ICFi bit is set
2.
An access (read or write) to the ICiLR register
OCMP1 = OLVL1
When counter = OC1R
When event occurs
OCMP1 = OLVL2
Counter is reset
to FFFCh
ICF1 bit is set
ICR1 = Counter
on ICAP1



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