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ST72325AR7-Auto датащи(PDF) 72 Page - STMicroelectronics

номер детали ST72325AR7-Auto
подробное описание детали  SCI asynchronous serial interface
PDF  243 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST72325AR7-Auto датащи(HTML) 72 Page - STMicroelectronics

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Obsolete
Product(s)
- Obsolete
Product(s)
Power saving modes
ST72325xxx-Auto
72/243
Doc ID 13770 Rev 3
Figure 30.
Halt mode flowchart
1.
WDGHALT is an option bit. See Section 21.1.1: Flash configurationfor more details.
2.
Peripheral clocked with an external clock source can still be active.
3.
Only some specific interrupts can exit the MCU from Halt mode (such as external interrupt). Refer to
Table 21: Interrupt mappingfor more details.
4.
Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are
set to the current software priority level of the interrupt routine and recovered when the CC register is
popped.
HALT INSTRUCTION
RESET
INTERRUPT (3)
Y
N
N
Y
CPU
OSCILLATOR
PERIPHERALS (2)
I[1:0] BITS
OFF
OFF
10
OFF
FETCH RESET VECTOR
OR SERVICE INTERRUPT
CPU
OSCILLATOR
PERIPHERALS
I[1:0] BITS
ON
OFF
XX (4)
ON
CPU
OSCILLATOR
PERIPHERALS
I[1:0] BITS
ON
ON
XX (4)
ON
256 OR 4096 CPU CLOCK
DELAY
WATCHDOG
ENABLE
DISABLE
WDGHALT (1)
0
WATCHDOG
RESET
1
(MCCSR.OIE = 0)
CYCLE



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