ST72321BARX datasheet(58/187 Pages) STMICROELECTRONICS

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ST72321BRx, ST72321BARx ST72321BJx, ST72321BKx

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MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (Cont’d)

10.2.5 Low Power Modes

10.2.6 Interrupts

The MCC/RTC interrupt event generates an inter-

rupt if the OIE bit of the MCCSR register is set and

the interrupt mask in the CC register is not active

(RIM instruction).

Note:

The MCC/RTC interrupt wakes up the MCU from

ACTIVE-HALT mode, not from HALT mode.

10.2.7 Register Description

MCC CONTROL/STATUS REGISTER (MCCSR)

Read/Write

Reset Value: 0000 0000 (00h)

Bit 7 = MCO Main clock out selection

This bit enables the MCO alternate function on the

PF0 I/O port. It is set and cleared by software.

0: MCO alternate function disabled (I/O pin free for

general-purpose I/O)

1: MCO alternate function enabled (fCPU on I/O

port)

Note: To reduce power consumption, the MCO

function is not active in ACTIVE-HALT mode.

Bit 6:5 = CP[1:0] CPU clock prescaler

These bits select the CPU clock prescaler which is

applied in the different slow modes. Their action is

conditioned by the setting of the SMS bit. These

two bits are set and cleared by software

Bit 4 = SMS Slow mode select

This bit is set and cleared by software.

0: Normal mode. fCPU = fOSC2

1: Slow mode. fCPU is given by CP1, CP0

See Section 8.2 SLOW MODE and Section 10.2

MAIN CLOCK CONTROLLER WITH REAL TIME

CLOCK AND BEEPER (MCC/RTC) for more de-

tails.

Bit 3:2 = TB[1:0] Time base control

These bits select the programmable divider time

base. They are set and cleared by software.

A modification of the time base is taken into ac-

count at the end of the current period (previously

set) to avoid an unwanted time shift. This allows to

use this time base as a real time clock.

Bit 1 = OIE Oscillator interrupt enable

This bit set and cleared by software.

0: Oscillator interrupt disabled

1: Oscillator interrupt enabled

This interrupt can be used to exit from ACTIVE-

HALT mode.

When this bit is set, calling the ST7 software HALT

instruction enters the ACTIVE-HALT power saving

mode.

Mode

Description

WAIT

No effect on MCC/RTC peripheral.

MCC/RTC interrupt cause the device to exit

from WAIT mode.

ACTIVE-

HALT

No effect on MCC/RTC counter (OIE bit is

set), the registers are frozen.

MCC/RTC interrupt cause the device to exit

from ACTIVE-HALT mode.

HALT

MCC/RTC counter and registers are frozen.

MCC/RTC operation resumes when the

MCU is woken up by an interrupt with “exit

from HALT” capability.

Interrupt Event

Event

Flag

Enable

Control

Bit

Exit

from

Wait

Exit

from

Halt

Time base overflow

event

OIF

OIE

Yes

No 1)

MCO

CP1

CP0

SMS

TB1

TB0

OIE

OIF

fCPU in SLOW mode

CP1

CP0

fOSC2 / 2

fOSC2 / 4

fOSC2 / 8

fOSC2 / 16

Counter

Prescaler

Time Base

TB1

TB0

fOSC2 =4MHz fOSC2=8MHz

16000

4ms

2ms

32000

8ms

4ms

80000

20ms

10ms

200000

50ms

25ms

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