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ST10F296 датащи(PDF) 310 Page - STMicroelectronics |
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ST10F296 датащи(HTML) 310 Page - STMicroelectronics |
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310 / 346 page ![]() Obsolete Product(s) - Obsolete Product(s) Electrical characteristics ST10F296E 310/346 24.7.5 Example of external network sizing This section provides an example of how to design an external network, based on realistic values for the internal parameters and on a hypothesis concerning the characteristics of the analog signal to be sampled. The following hypothesis is formulated to design the external network on the ADC input pins: – Analog signal source bandwidth (f0): 10 kHz – Conversion rate (fC): 25 kHz – Sampling time (TS): 1 µs – Pin input capacitance (CP1): 5 pF – Pin input routing capacitance (CP2): 1 pF – Sampling capacitance (CS): 4 pF – Maximum input current injection (IINJ): 3 mA – Maximum analog source voltage (VAM): 12 V – Analog source impedance (RS): 100 Ω – Channel switch resistance (RSW): 500 Ω – Sampling switch resistance (RAD): 200 Ω If designing a filter with the pole at the maximum frequency of the signal, the time constant of the filter is given in Equation 34: Equation 34 Using the relationship between CF and CS (Equation 33) and taking some margin (4000 instead of 2048), it is possible to define CF as shown in Equation 35. Equation 35 Equation 34 and Equation 35 allow the RC to be calculated as shown in Equation 36. Equation 36 Total series resistance can be calculated using Equation 37 where the current injection limitation is considered and it is assumed that the source can go up to 12 V. Equation 37 Equation 37 allows a value for RL to be defined as shown in Equation 38. R CCF 12 πf 0 () ⁄ 15.9 µs == C F 4000 C S × 16nF == R F 12 πf 0CF () ⁄ 995 Ω 1kΩ ≅ == R S R F R L ++ V AM I INJ ⁄ 4k Ω == Obsolete Product(s) - Obsolete Product(s) |
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