ST10F296 datasheet(284/346 Pages) STMICROELECTRONICS

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RP0H register

RP0H is a read-only register.

RP0H (F108h/84h)

ESFR

Reset value: --XXh

----

CLKSEL

SALSEL

CSSEL

WRC

----

R(1)(2)

Bits 7 to 5 of the RP0H register are loaded only during a long hardware reset. As pull-up resistors are

active on each Port P0H pins during reset, the RP0H default value is FFh.

Bits 7 to 0 of the RP0H register are set according to Port 0 configuration during any reset sequence.

R(2)

Table 152.

RP0H register description

Bit

Bit name

Function

7-5

CLKSEL

System clock selection

000: fCPU = 16 x fOSC

001: fCPU = 0.5 x fOSC

010: fCPU = 10 x fOSC

011: fCPU = fOSC

100: fCPU = 5 x fOSC

101: fCPU = 8 x fOSC

110: fCPU = 3 x fOSC

111: fCPU = 4 x fOSC

4-3

SALSEL

Segment address line selection (number of active segment address

outputs)

00: 4-bit segment addresses, A19 to A16.

01: No segment address lines.

10: 8-bit segment addresses, A23 to A16.

11: 2-bit segment address, A17 and A16 (default without pull-downs).

2-1

CSSEL

Chip select line selection (number of active CS outputs)

00: Three CS lines, CS2 to CS0.

01: Two CS lines, CS1 and CS0.

10: No CS lines.

11: Five CS lines, CS4 to CS0 (default without pull-downs)

0WRC

Write configuration control

0: WR and BHE pins behave as WRL and WRH pins respectively.

1: WR and BHE pins retain their normal functioning.

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