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ST10F296 датащи(PDF) 283 Page - STMicroelectronics |
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ST10F296 датащи(HTML) 283 Page - STMicroelectronics |
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283 / 346 page ![]() Obsolete Product(s) - Obsolete Product(s) ST10F296E Register set 283/346 Table 151. BUSCONx register description Bit Bit name Function 15 CSWENx Write chip select enable 0: The CS signal is independent of the write command (WR, WRL, WRH). 1: The CS signal is generated for the duration of the write command. 14 CSRENx Read chip select enable 0: The CS signal is independent of the read command (RD). 1: The CS signal is generated for the duration of the read command. 13 RDYPOLx Ready active level control 0: Active level on the READY pin is low and he bus cycle terminates with an 0 on this pin. 1: Active level on the READY pin is high and the bus cycle terminates with a 1 on this pin. 12 RDYENx READY input enable 0: External bus cycle is controlled by the MCTC bit field. 1: External bus cycle is controlled by the READY input signal. 10 BUSACTx Bus active control 0: External bus disabled. 1: External bus enabled (within the respective address window, see ADDRSEL register. 9ALECTLx ALE lengthening control 0: Normal ALE signal. 1: Lengthened ALE signal. 7-6 BTYP External bus configuration 00: 8-bit demultiplexed bus 01: 8-bit multiplexed bus 10: 16-bit demultiplexed bus 11: 16-bit multiplexed bus Note 1: BTYP bits of BUSCON0 are defined via Port 0 during reset. They are set according to the configuration of bit 6 and 7 of Port 0 latched at the end of the reset sequence. Note 2: If the EA pin is high during reset, the BUSCON0 register is initialized with 0000h. If EA pin is low during reset, the BUSACT0 and ALECTL0 bits are set (1) and the BTYP bit field is loaded with the bus configuration selected via Port 0. 5MTTCx Memory tristate time control 0: 1 wait state. 1: No wait state. 4 RWDCx Read/write delay control for BUSCONx 0: With read/write delay, the CPU inserts 1 TCL after falling edge of ALE. 1: No read/write delay; RW is activated after falling edge of ALE. 3-0 MCTC Memory cycle time control (number of memory cycle time wait states) 0000: 15 wait states (number of wait states = 15 - [MCTC]). . . . 1111: No wait states. Obsolete Product(s) - Obsolete Product(s) |
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