ST10F296 datasheet(205/346 Pages) STMICROELECTRONICS

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ST10F296E

Real-time clock (RTC)

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18.1

RTC registers

RTC control register (RTCCON)

The functions of the RTC are controlled by the RTCCON control register (see register table

and description below). If the RTOFF bit is set, the RTC dividers and counter clocks are

disabled and the registers can be written. When the ST10 chip enters power-down mode,

the clock oscillator is switched off. The RTC has two interrupt sources: One is triggered

every basic clock period, the other is the alarm.

Note:

The RTC registers are not bit-addressable.

The RTCCON register includes an interrupt request flag and an interrupt enable bit for each

interrupt source. This register is read and written via the XBus.

RTCCON (ED00h)

XBus

Reset value: --00h

987

65432

---

-----

RTC

OFF

---

RTC

AEN

RTC

AIR

RTC

SEN

RTC

SIR

---

-----

Table 124.

RTCCON register description

Bit

Bit name

Function

7RTCOFF(1)

The two RTC interrupt signals are connected to Port 2 to trigger an external interrupt that can wake up the

chip when in power-down mode.

RTC switch off bit

0: Clock oscillator and RTC keep running even if ST10 is in power-

down mode.

1: If ST10 enters power-down mode, clock oscillator is switched off,

RTC dividers and counters are stopped, and registers can be

written.

RTCAEN

RTC alarm interrupt enable

0: RTCAI is disabled

1: RTCAI is enabled; it is generated when the counters reach the

alarm value.

2RTCAIR(2)(3)

To clear the RTC interrupt request flags (bit 0 and bit 2 of the RTCCON register) it is necessary to write a 1

to the corresponding bit of the RTCCON register.

As the RTCCON register is not bit-addressable, the value of its bits must be read by checking their

associated CCxIC register.

RTC alarm interrupt request flag (when the alarm is triggered)

0: RTCAIR bit is reset in less than an n basic clock tick.

1: An interrupt is triggered

RTCSEN

RTC second interrupt enable

0: RTCSI is disabled

1: RTCSI is enabled; it is generated every basic clock tick

0RTCSIR(2)(3)

RTC second interrupt request flag (every second)

0: RTCSIR bit is reset in less than an a basic clock tick.

1: An interrupt is triggered

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