ST7MC1K2-Auto datasheet(172/371 Pages) STMICROELECTRONICS

172 / 371 page

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ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto, ST7MC2S6-Auto

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SCI control register 2 (SCICR2)

Word length

This bit determines the word length. It is set or cleared by software.

0: 1 start bit, 8 data bits, 1 stop bit

1: 1 start bit, 9 data bits, 1 stop bit

Note: The M bit must not be modified during a data transfer (both transmission and

reception).

3WAKE

Wake-up method

This bit determines the SCI wake-up method. It is set or cleared by software.

0: Idle line

1: Address mark

Note: If the LINE bit is set, the WAKE bit is deactivated and replaced by the LHDM bit.

2PCE

Parity control enable

This bit is set and cleared by software. It selects the hardware parity control for LIN

identifier parity check.

0: Parity control disabled

1: Parity control enabled

When a parity error occurs, the PE bit in the SCISR register is set.

Reserved, must be kept cleared

0PIE

Parity interrupt enable

This bit enables the interrupt capability of the hardware parity control when a parity

error is detected (PE bit set). The parity error involved can be a byte parity error (if bit

PCE is set and bit LPE is reset) or a LIN parity error (if bit PCE is set and bit LPE is

set).

0: Parity error interrupt disabled

1: Parity error interrupt enabled

Bits 7:3 and bit 0 have the same function as in SCI mode; please refer to SCI control register 1 (SCICR1)

on page 153.

SCICR2

Reset value: 0000 0000 (00h)

654

TIE

TCIE

RIE

ILIE

RWU

SBK

R/W

Table 70.

SCICR2 register description(1)

Bit Name

Function

TIE

Transmitter interrupt enable

This bit is set and cleared by software.

0: Interrupt is inhibited

1: An SCI interrupt is generated whenever TDRE = 1 in the SCISR register

6TCIE

Transmission complete interrupt enable

This bit is set and cleared by software.

0: Interrupt is inhibited

1: An SCI interrupt is generated whenever TC = 1 in the SCISR register

Table 69.

SCICR1 register description(1) (continued)

Bit Name

Function

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