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ST7MC1K2-Auto датащи(PDF) 169 Page - STMicroelectronics

номер детали ST7MC1K2-Auto
подробное описание детали  Clock, reset and supply management
PDF  371 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST7MC1K2-Auto датащи(HTML) 169 Page - STMicroelectronics

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On-chip peripherals
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Error due to baud rate quantization
The baud rate can be adjusted in steps of 1/(16 * LDIV). The worst case occurs when the
‘real’ baud rate is in the middle of a step.
This leads to a quantization error (DQUANT) equal to 1/(2*16*LDIVMIN).
Impact of clock deviation on maximum baud rate
The choice of the nominal baud rate (LDIVNOM) influences both the quantization error
(DQUANT) and the measurement error (DMEAS). The worst case occurs for LDIVMIN.
Consequently, at a given CPU frequency, the maximum possible nominal baud rate
(LPRMIN) should be chosen with respect to the maximum tolerated deviation given by the
equation:
DTRA + 2/(128*LDIVMIN) + 1/(2*16*LDIVMIN) + DREC + DTCL <3.75%
Example:
A nominal baud rate of 20Kbits/s at TCPU = 125ns (8 MHz) leads to LDIVNOM = 25d.
LDIVMIN = 25 - 0.15*25 = 21.25
DMEAS = 2/(128*LDIVMIN) * 100 = 0.00073%
DQUANT =1/(2*16*LDIVMIN) * 100 = 0.0015%
LIN slave systems
For LIN slave systems (the LINE and LSLV bits are set), receivers wake up by LIN synch
break or LIN identifier detection (depending on the LHDM bit).
Hot plugging feature for LIN slave nodes
In LIN slave mute mode (the LINE, LSLV and RWU bits are set) it is possible to hot plug to a
network during an ongoing communication flow. In this case the SCI monitors the bus on the
RDI line until 11 consecutive dominant bits have been detected and discards all the other
bits received.
10.5.10
LIN mode registers
SCI status register (SCISR)
SCISR
Reset value: 1100 0000 (C0h)
7
654
32
10
TDRE
TC
RDRF
IDLE
LHE
NF
FE
PE
RO
RO
RO
RO
RO
RO
RO
RO
Obsolete
Product(s)
- Obsolete
Product(s)



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