ST7MC1K2-Auto datasheet(170/371 Pages) STMICROELECTRONICS

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Table 68.

SCISR register description(1)

Bit Name

Function

TDRE

Transmit data register empty

This bit is set by hardware when the content of the TDR register has been transferred

into the shift register. An interrupt is generated if the TIE = 1 in the SCICR2 register. It

is cleared by a software sequence (an access to the SCISR register followed by a

write to the SCIDR register).

0: Data is not transferred to the shift register

1: Data is transferred to the shift register

6TC

Transmission complete

This bit is set by hardware when transmission of a character containing data is

complete. An interrupt is generated if TCIE = 1 in the SCICR2 register. It is cleared by

a software sequence (an access to the SCISR register followed by a write to the

SCIDR register).

0: Transmission is not complete

1: Transmission is complete

Note: TC is not set after the transmission of a preamble or a break.

5RDRF

Received data ready flag

This bit is set by hardware when the content of the RDR register has been transferred

to the SCIDR register. An interrupt is generated if RIE = 1 in the SCICR2 register. It is

cleared by a software sequence (an access to the SCISR register followed by a read

to the SCIDR register).

0: Data is not received

1: Received data is ready to be read

4IDLE

Idle line detected

This bit is set by hardware when an idle line is detected. An interrupt is generated if

the ILIE = 1 in the SCICR2 register. It is cleared by a software sequence (an access to

the SCISR register followed by a read to the SCIDR register).

0: No idle line is detected

1: idle line is detected

Note: The idle bit is not set again until the RDRF bit has been set itself (that is, a new

idle line occurs).

3LHE

LIN header error

During LIN header this bit signals three error types:

The LIN synch field is corrupted and the SCI is blocked in LIN Synch state (LSF

bit = 1).

A timeout occurred during LIN header reception.

An overrun error was detected on one of the header field (see OR bit description in

SCI status register (SCISR) on page 152).

An interrupt is generated if RIE = 1 in the SCICR2 register. If blocked in the LIN synch

state, the LSF bit must first be reset (to exit LIN synch field state and then to be able to

clear LHE flag). Then it is cleared by the following software sequence: An access to

the SCISR register followed by a read to the SCIDR register.

0: No LIN Header error

1: LIN Header error detected

Note: Apart from the LIN header this bit signals an overrun error as in SCI mode, (see

description in SCI status register (SCISR) on page 152).

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