ST7LITE49K2 datasheet(30/245 Pages) STMICROELECTRONICS

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Data EEPROM

ST7LITE49K2

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5.3

Memory access

The Data EEPROM memory read/write access modes are controlled by the E2LAT bit of the

EEPROM Control/Status register (EECSR). The flowchart in Figure 7 describes these

different memory access modes.

5.3.1

Read operation (E2LAT=0)

The EEPROM can be read as a normal ROM location when the E2LAT bit of the EECSR

On this device, Data EEPROM can also be used to execute machine code. Take care not to

write to the Data EEPROM while executing from it. This would result in an unexpected code

being executed.

5.3.2

Write operation (E2LAT=1)

To access the write mode, the E2LAT bit has to be set by software (the E2PGM bit remains

cleared). When a write access to the EEPROM area occurs, the value is latched inside the

32 data latches according to its address.

When PGM bit is set by the software, all the previous bytes written in the data latches (up to

32) are programmed in the EEPROM cells. The effective high address (row) is determined

by the last EEPROM write sequence. To avoid wrong programming, the user must take care

that all the bytes written between two programming sequences have the same high address:

only the five Least Significant Bits of the address can change.

At the end of the programming cycle, the PGM and LAT bits are cleared simultaneously.

Note:

Care should be taken during the programming cycle. Writing to the same memory location

will over-program the memory (logical AND between the two write access data result)

because the data latches are only cleared at the end of the programming cycle and by the

falling edge of the E2LAT bit. It is not possible to read the latched data (see Figure 9).

Figure 7.

Data EEPROM programming flowchart

READ MODE

E2LAT=0

E2PGM=0

WRITE MODE

E2LAT=1

E2PGM=0

READ BYTES

IN EEPROM AREA

WRITE UP TO 32 BYTES

IN EEPROM AREA

(with the same 11 MSB of the address)

START PROGRAMMING CYCLE

E2LAT=1

E2PGM=1 (set by software)

E2LAT

CLEARED BY HARDWARE

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