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ST7LITE49K2 датащи(PDF) 162 Page - STMicroelectronics

номер детали ST7LITE49K2
подробное описание детали  Communication interfaces
PDF  245 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
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ST7LITE49K2 датащи(HTML) 162 Page - STMicroelectronics

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Figure 77.
Data clock timing diagram
11.6.6
Error flags
Master mode fault (MODF)
Master mode fault occurs when the master device’s SS pin is pulled low.
When a Master mode fault occurs:
●
The MODF bit is set and an SPI interrupt request is generated if the SPIE bit is set.
●
The SPE bit is reset. This blocks all output from the device and disables the SPI
peripheral.
●
The MSTR bit is reset, thus forcing the device into slave mode.
Clearing the MODF bit is done through a software sequence:
SCK
MSBit
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
LSBit
MSBit
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
LSBit
MISO
(from master)
MOSI
(from slave)
SS
(to slave)
CAPTURE STROBE
CPHA = 1
MSBit
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
LSBit
MSBit
Bit 6
Bit 5
Bit 4
Bit3Bit 2Bit 1
LSBit
MISO
(from master)
MOSI
SS
(to slave)
CAPTURE STROBE
CPHA = 0
Note: This figure should not be used as a replacement for parametric information.
Refer to the Electrical Characteristics chapter.
(from slave)
(CPOL = 1)
SCK
(CPOL = 0)
SCK
(CPOL = 1)
SCK
(CPOL = 0)



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