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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ST7LITE49K2 датащи(PDF) 111 Page - STMicroelectronics |
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ST7LITE49K2 датащи(HTML) 111 Page - STMicroelectronics |
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111 / 245 page  ST7LITE49K2 On-chip peripherals 111/245 11.3.4 Low power modes 11.3.5 Interrupts The TBxF and ICF interrupt events are connected to the same interrupt vector (see Section 8: Interrupts). They generate an interrupt if the enable bit is set in the LTCSR1 or LTCSR2 register and the interrupt mask in the CC register is reset (RIM instruction). 11.3.6 Register description Lite timer control/status register 2 (LTCSR2) Reset value: 0000 0000 (00h) Bits 7:2 = Reserved, must be kept cleared. Bit 1 = TB2IE Timebase 2 Interrupt enable bit This bit is set and cleared by software. 0: Timebase (TB2) interrupt disabled 1: Timebase (TB2) interrupt enabled Table 39. Effect of low power modes on Lite timer 2 Mode Description Slow No effect on Lite timer (this peripheral is driven directly by fOSC/32) Wait No effect on Lite timer Active-halt No effect on Lite timer Halt Lite timer stops counting Table 40. Description of interrupt events Interrupt Event Event Flag Enable Control Bit Exit from Wait Exit from Active-halt Exit from Halt Timebase 1 Event TB1F TB1IE Yes Yes No Timebase 2 Event TB2F TB2IE No IC Event ICF ICIE No 7 0 00000 0 TB2IE TB2F Read / Write |
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