SPC560P50L5 datasheet(24/112 Pages) STMICROELECTRONICS

24 / 112 page

Introduction

SPC560P44Lx, SPC560P50Lx

24/112

Doc ID 14723 Rev 9

The FlexPWM block implements the following features:

●

16-bit resolution for center, edge-aligned, and asymmetrical PWMs

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Maximum operating clock frequency of 120 MHz

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PWM outputs can operate as complementary pairs or independent channels

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Can accept signed numbers for PWM generation

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Independent control of both edges of each PWM output

●

Synchronization to external hardware or other PWM supported

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Double buffered PWM registers

–

Integral reload rates from 1 to 16

–

Half cycle reload capability

●

Multiple ADC trigger events can be generated per PWM cycle via hardware

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Write protection for critical registers

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Fault inputs can be assigned to control multiple PWM outputs

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Programmable filters for fault inputs

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Independently programmable PWM output polarity

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Independent top and bottom deadtime insertion

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Each complementary pair can operate with its own PWM frequency and deadtime

values

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Individual software-control for each PWM output

●

All outputs can be programmed to change simultaneously via a “Force Out” event

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PWMX pin can optionally output a third PWM signal from each submodule

●

Channels not used for PWM generation can be used for buffered output compare

functions

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Channels not used for PWM generation can be used for input capture functions

●

Enhanced dual-edge capture functionality

●

eDMA support with automatic reload

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2 fault inputs

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Capture capability for PWMA, PWMB, and PWMX channels not supported

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