SPC560P50L5 datasheet(111/112 Pages) STMICROELECTRONICS

111 / 112 page

SPC560P44Lx, SPC560P50Lx

Revision history

Doc ID 14723 Rev 9

111/112

18-Jul-2012

Updated

Table 1 (Device summary)

Section 1.5.4, Flash memory: Changed “Data flash memory: 32-bit ECC” to “Data flash

memory: 64-bit ECC”

Figure 40 (Commercial product code structure), replaced "C = 60 MHz, 5 V" and "D = 60

MHz, 3.3 V" with respectively "C = 40 MHz, 5 V" and "D = 40 MHz, 3.3 V"

Table 9 (Absolute maximum ratings), updated TVDD parameter, the minimum value to

3.0 V/s and the maximum value to 0.5 V/µs

Table 7 (Pin muxing), changed the description in the column "I/O direction" from "I/O" to

"O" for the following port pins:

A[10] with function B[0]

A[11] with function A[0]

A[11] with function A[2]

A[12] with function A[2]

A[12] with function B[2]

A[13] with function B[2]

C[7] with function A[1]

C[10] with function A[3]

C[15] with function A[1]

D[0] with function B[1]

D[10] with function A[0]

D[11] with function B[0]

D[13] with function A[1]

D[14] with function B[1]

Updated Section 3.8.1, Voltage regulator electrical characteristics

Added

Table 27 (I/O consumption)

Section 3.10, DC electrical characteristics:

deleted references to “oscillator margin”

deleted subsection “NVUSRO[OSCILLATOR_MARGIN] field description”

Table 21 (DC electrical characteristics (5.0 V, NVUSRO[PAD3V5V] = 0)), added IPU row

for RESET pin

Table 23 (DC electrical characteristics (3.3 V, NVUSRO[PAD3V5V] = 1)), added IPU row

for RESET pin

Table 33 (ADC conversion characteristics), added VINAN entry

Removed “Order codes” table

Figure 40 (Commercial product code structure):

added a footnote

updated “E = Data flash memory”

18-Sep-2013

Updated Disclaimer

Table 46.

Revision history (continued)

Date

Revision

Changes

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