SPC56EL54X datasheet(12/165 Pages) STMICROELECTRONICS

12 / 165 page

Introduction

SPC56ELx, SPC564Lx

12/165

DocID15457 Rev 12



High-performance e200z4d dual core

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32-bit Power Architecture® technology CPU

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Core frequency as high as 120 MHz

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Dual issue five-stage pipeline core

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Variable Length Encoding (VLE)

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Memory Management Unit (MMU)

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4 KB instruction cache with error detection code

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Signal processing engine (SPE)



Memory available

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1 MB flash memory with ECC

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128 KB on-chip SRAM with ECC

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Built-in RWW capabilities for EEPROM emulation



SIL3/ASILD innovative safety concept: LockStep mode and Fail-safe protection

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Sphere of replication (SoR) for key components (such as CPU core, eDMA,

crossbar switch)

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Fault collection and control unit (FCCU)

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Redundancy control and checker unit (RCCU) on outputs of the SoR connected to

FCCU

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Boot-time Built-In Self-Test for Memory (MBIST) and Logic (LBIST) triggered by

hardware

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Boot-time Built-In Self-Test for ADC and flash memory triggered by software

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Replicated safety enhanced watchdog

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Replicated junction temperature sensor

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Non-maskable interrupt (NMI)

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16-region memory protection unit (MPU)

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Clock monitoring units (CMU)

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Power management unit (PMU)

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Cyclic redundancy check (CRC) unit

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Decoupled Parallel mode for high-performance use of replicated cores

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Nexus Class 3+ interface

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Interrupts

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Replicated 16-priority controller

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Replicated 16-channel eDMA controller

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GPIOs individually programmable as input, output or special function

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Three 6-channel general-purpose eTimer units

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2 FlexPWM units

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Four 16-bit channels per module



Communications interfaces

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2 LINFlexD channels

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3 DSPI channels with automatic chip select generation

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2 FlexCAN interfaces (2.0B Active) with 32 message objects

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