PM6675 datasheet(19/47 Pages) STMICROELECTRONICS

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PM6675

Device description

19/47

The design of the external feedback network depends on the output voltage ripple. If the

ripple is higher than approximately 20mV, the correct CINT capacitor is usually enough to

keep the loop stable. The stability of the system depends firstly on the output capacitor zero

frequency.

The following condition must be satisfied:

Equation 6

where k is a fixed design parameter (k > 3). It determinates the minimum integrator

capacitor value:

Equation 7

where gm = 50

µs is the integrator trans conductance.

If the ripple on the COMP pin is greater than the integrator 150mV, the auxiliary capacitor

CFILT can be added. If q is the desired attenuation factor of the output ripple, CFILT is given

by:

Equation 8

In order to reduce the noise on the COMP pin, it is possible to add a resistor RINT that,

together with CINT and CFILT, becomes a low pass filter. The cutoff frequency fCUT must be

much greater (10 or more times) than the switching frequency:

Equation 9

If the ripple is very small (lower than approximately 20mV), a different compensation

network, called "Virtual-ESR" Network, is needed. This additional circuit generates a

triangular ripple that is added to the output voltage ripple at the input of the integrator. The

complete control scheme is shown in Figure 8.

ESR

out

Zout

⋅

Vout

Zout

INT

⋅

⎟

⎠

⎞

⎜

⎝

⎛

−

⋅

)

(

INT

FILT

−

⋅

FILT

INT

FILT

INT

CUT

INT

⋅

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