SCANPSC110F datasheet(26/29 Pages) NSC

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Applications Example (Continued)

Assume that boards #6, #7 and #8 are identical, so that

it is possible to test them simultaneously. The tester first

addresses Board #6. Next the

MCGRSELinstruction is

issued to place the Multi-Cast Group register into the ac-

tive scan chain, and the binary value “01” is shifted into

the MCGR. The

GOTOWAIT instruction is then issued

returning all ’PSC110F’s to the

Wait-For-Address state.

The MCGR for ’PSC110F #7 and ’PSC110F #8 are pro-

grammed the same as Board #6. Next the Multi-Cast ad-

dress “00111101” is issued by the tester, which causes

the ’PSC110F Selection controller of ’PSC110F #6–#8

to enter the

Selected-Multi-Cast state. The LFSRON in-

struction is then issued to enable the signature compac-

tion circuitry on the selected ’PSC110Fs. The

SAMPLE/

PRELOAD and EXTEST instructions are then used to

test the interconnects, similar to steps 4 and 5 above.

When the test sequence is complete, the

GOTOWAIT

instruction is issued returning all ’PSC110Fs to the

Wait-For-Address state . ’PSC110Fs #6, #7, and #8 are

then addressed one at a time to read back the test sig-

nature from the LFSR (the LFSR is read by selecting it

with the

LFSRSEL instruction, then scanning out its con-

tents.

After testing the interconnect on the individual boards,

the next step is to test the backplane interconnect. This

is a pair-wise test between Board #1 and each of the

other boards. Board #1 drives test patterns onto th back-

plane wiring, and the currently addressed slave board

senses the written data via its backplane scan interface.

In this example, the interconnect between Board #1 and

Board #2 is tested first. To test this interconnect, the

1149.1-compliant

backplane

transceivers,

SCAN182245A, SCAN ABT Test Access Logic, on each

board must be accessed for scan operations (see

Figure

19 ). For more information on SCAN ABT live insertion

capabilities, refer to the SCAN182245A datasheet.

First, the system master (Board #1) is addressed and

selected. The 1149.1-compliant SCAN ABT transceivers

reside on the chain connected to LSP

2 on Board #1. The

mode register is re-configured so that only port LSP

2 is

in the chain, and the

UNPARK instruction is then used to

access this chain. The appropriate instruction register

and data register scan sequencing is then performed to

apply a pattern to the backplane using the SCAN ABT

bus transceiver.

10. To test the backplane interconnect, LSP

2 of Board #1

must be parked in the

Run-Test/Idle TAP controller

state, so that the EXTEST command will stay active

when Board #1 is de-selected (the

PARKRTI instruction

is issued). The

GOTOWAIT instruction is then issued to

return all boards to the

Wait-For-Address state. Each

one of the slave boards is then addressed, one at a

time, to sample the backplane signals being driven by

Board #1. For example, Board #2 is addressed. The

mode register is reconfigured, (if needed), to select the

scan chain (LSP

2) that includes the SCAN ABT back-

plane transceivers for Board #2. The

UNPARK instruc-

tion is issued to unpark LSP

n and insert it into the active

scan chain. The

SAMPLE/PRELOAD instruction is is-

sued to the SCAN ABT backplane transceivers, (

BY-

PASS to other components in the scan chain). The

backplane is sampled by sequencing the TAP controller

through the

Capture-DR state and the data is shifted out

and checked by the tester. The

PARKRTI instruction is

then given to park LSP

n of Board #2inthe Run-Test/Idle

state, and the

GOTOWAIT instruction is issued to return

all ’PSC110Fs to the

Wait-For-Address state so that the

next board, (Board #3), can be sampled. This procedure

is repeated for boards #3–#8, then Board #1 is selected

again, a new pattern is shifted out and driven by the

EX-

TEST command, and the slave boards are again

sampled.

11. Step 10 is repeated until the backplane interconnect has

been sufficiently tested.

12. When testing is complete, the controller sends out the

SOFTRESET instruction to all ’PSC110Fs. This is ac-

complished by first using the broadcast address, “3B”

Hex, to select all ’PSC110Fs. The

SOFTRESET com-

mand is then loaded, causing TMS

L(1–3) signals to go

high; this drives all local TAPs into the

Test-Logic-Reset

state within five TCK cycles.

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