DocID025003 Rev 1

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A6727

Application information

10.2

Output capacitors

Output capacitor choice depends on the output voltage ripple and the output voltage

deviation during a load transient.

During steady-state conditions, the output voltage ripple is influenced by both ESR and

capacitive value of the output capacitors as follows:

Equation 9

Equation 10

Where

than the sum of their modules. Both ESL and board parasitic inductance can contribute to

the output ripple significantly.

During a load variation, the output capacitors supply the load with the current or absorb the

current in excess delivered by the inductor until converter reaction is completed. In fact,

even if the controller reacts immediately to the load transient saturating the duty cycle to

80% or 0%, the current slew rate is limited by the inductance. The output voltage drop,

based on ESR and capacitive charge/discharge and considering an ideal load-step, can be

estimated as follows:

Equation 11

Equation 12

Where

MLCC capacitors typically have low ESR to minimize the ripple but also have low

capacitance which doesn’t minimize the voltage deviation during the load transient. On

contrary, electrolytic capacitors usually have higher capacitance to minimize capacitive

voltage deviation during the load transient, but also higher ESR value resulting in higher

ripple voltage and resistive voltage drop. For these reasons, a mix between the electrolytic

and MLCC capacitor is suggested so to minimize the ripple and reduce the voltage deviation

in dynamic mode.

ΔV

OUT_ESR

ΔI

L

ESR

⋅

=

ΔV

OUT_C

ΔI

L

1

8C

OUT

F

SW

⋅⋅

---------------------------------------

⋅

=

ΔV

OUT_ESR

ΔI

OUT

ESR

⋅

=

ΔV

OUT_C

L

ΔI

OUT

2

⋅

2C

OUT

ΔV

L

⋅⋅

--------------------------------------

=

D

MAX

V

IN

V

OUT

–

⋅