Application details

A6727

20/29

DocID025003 Rev 1

high-current trace on more than one PCB layer reduces the parasitic resistance associated

to that connection.

minimizing parasitic inductance and resistance associated to the copper trace.

Figure 10. Power connections (heavy lines)

Gate traces and phase trace must be sized according to the driver RMS current delivered to

the power MOSFET. The device robustness allows the management of applications with the

power section far from the controller without losing performances. Anyway, when possible,

the distance between the controller and the power section has to be minimized. See

Figure 11 for driver current paths.

Small signal components and connections to critical nodes of the application, as well as

bypass capacitors for the device supply, are also important. Locate bypass capacitor (VCC

and bootstrap capacitor) and loop compensation components close to the device. With

leakage current paths on COMP/OC pin, since the internal current source is only 60 mA.

Systems, which do not use the Schottky diode in parallel to the low-side MOSFET, might

show big negative spikes on the phase pin. This spike must be limited within the absolute

maximum ratings (for example, adding a gate resistor in series to HS MOSFET gate, or a

phase resistor in series to PHASE pin), as well as the positive spike.The further

consequence is that the bootstrap capacitor is overcharged. This extra-charge can cause, in

the worst case, a condition of maximum input voltage and during particular transients,

BOOT-to-PHASE voltage overcomes the absolute maximum ratings causing device failures.

This extra-charge has to be limited by adding a small resistor in series to the bootstrap

L

UGATE

PHASE

LGATE

GND

LOAD

A6727

AM16774v1