TMS320VC5441 datasheet(13/91 Pages) TI1

13 / 91 page

Introduction

December 1999 − Revised October 2008

SPRS122F

2.2

Migration From the 5421 to the 5441

Customers who are migrating from the 5421 to the 5441 need to take into account the following differences

between the two devices.

•

The 5441 provides four cores in a 169-ball ball grid array (BGA) and a 176-pin low-profile quad flatpack

(LQFP).

•

The 5441 does not have a XIO interface for external memory connection.

•

Each subsystem includes a 32K-word DARAM program/data memory and a 64K-word DARAM data

memory.

•

The DMA has been changed and now provides no access to external memory.

•

The HPI and DMA memory maps have been changed to incorporate the new 5441 memory structure.

•

The 2K words of ROM on the 5421 is not implemented on the 5441.

•

The four McBSP1s and four McBSP2s have been internally multiplexed onto two sets of external pins.

•

The HPI_SEL1 and HPI_SEL2 pins on 5441 are used to facilitate HPI module selection among the four

subsystems.

•

The 5441 provides four watchdog timers (one per subsystem).

•

GPIO0 and GPIO1 pins are multiplexed with x_XF and x_BIO pins, respectively.

•

Only the global reset (RESET) will reset the PLL.

2.3

Pin Assignments

Figure 2−1 illustrates the ball locations for the 169-ball ball grid array (BGA) package and is used in

conjunction with Table 2−1 to locate signal names and ball grid numbers. Figure 2−2 illustrates the pin

locations for the 176-pin low-profile quad flatpack (LQFP); Table 2−2 lists each pin number and its associated

pin name for this package.

2.3.1 Pin Assignments for the GGU Package

6 7 8 9 1011 1213

Figure 2−1. 169-Ball GGU MicroStar BGA

 (Bottom View)

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