PC87570 datasheet(141/168 Pages) NSC

141 / 168 page

141

Device Specifications

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tRDYA

19-16 IOCHRDY inactive

After HIOWR,

HMEMWR, HIORD

or HMEMRD FE

30 ns

GPIO Ports Input Signals

tINPs

19-15 Input setup time PA0-

6, PB0-7, PC0-7,

PD0-7, PE0,1, PF0-7,

PG0-4, PH0-5

Before RE CLK

0.5 * tCLK

tINPh

19-15 Input hold time PA0-

6, PB0-7, PC0-7,

PD0-7, PE0-1, PF0-7,

PG0-4, PH0-5

After RE CLK

GPIO Ports Output Signals

tOUTv

19-14 Output valid time

KBSOUT0-15, PA0-

6, PB0-7, PC0-7,

PE0-1, PF0-7, PG0-

4, PH0-5

After RE CLK

0.5 * tCLK

tOUTh

19-14 Output hold time

KBSOUT0-15, PA0-

6, PB0-7, PC0-7,

PE0-1, PF0-7, PG0-

4, PH0-5

After RE CLK

PS/2 Input Signals

tPSDIs

19-28 Input setup time

PSDAT1-3

Before FE PSCLK1-

tPSDIh

19-28 Input hold time

PSDAT1-3

After RE PSCLK1-3

tPSCLKl 19-28,

19-29

PSCLK1-3 low time

At 0.8V (both edges) (n + 1) * tCLK

(n + 1) * tCLK

tPSCLKh 19-28,

19-29

PSCLK1-3 high time

At 2.0V (both edges)

(n + 1) *

tCLK

(n + 1) * tCLK

PS/2 Output Signals

tPSDOv

19-29 Output valid time

PSDAT1-3

After FE PSCLK1-3

(n + 6) * tCLK

+ 14 ns4

(n + 6) * tCLK

+ 14 ns4

tPSCLKa 19-30 Output active time

PSCLK1-3

After RE CLK

14 ns

17 ns

tPSCLKia 19-30 Output inactive time

PSCLK1-3

After RE CLK

14 ns

17 ns

tRDYDv

19-16

HD0-7 valid

Before IOCHRDY

ACCESS.bus Input Signals

tBUFi

19-20 Bus free time

between Stop and

Start condition

tSCLhigho

tCSTOsi

19-20 SCL setup time

Before Stop

condition

8 * tCLK -

tSCLri

8 * tCLK -

tSCLri

Symbol Figure

Description

Reference

Conditions

VCC = 5 V 10%

VCC = 3.3 V ± 10%

Min

Max

Min

Max

PC87570 датащи(PDF) 141 Page - National Semiconductor (TI)

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