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PC87570 датащи(PDF) 143 Page - National Semiconductor (TI) |
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PC87570 датащи(HTML) 143 Page - National Semiconductor (TI) |
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143 / 168 page ![]() 143 Device Specifications www.national.com 1. K is the number of wait cycles added to the bus cycle. This number may be 0 or more. 2. In shared memory write operations, the actual write to memory is executed after HMEMWR is inactive. In case reset or entering Idle mode occurs before the memory write cycle is completed it may be that the data will not be written to memory. 3. n is the number of clock cycles, as programmed in the IDB field. See PS/2 Control Register in Section 12.5.3 on page 95. 4. n is the number of clock cycles, as programmed in the IDB field. See PS/2 Control Register in Section 12.5.3 on page 95. 5. Refer to Table 7-1 on page 76 for the definition of tCLKINTnom. 6. Depends on the signal capacitance and the pull-up value. 7. Assuming signal capacitance up to 400 pF. tSDAvo 19-22 SDA valid time After SCL FE 7 * tCLK + tRD 7 * tCLK + tRD MFT16 Input Signals tTAH 19-18 TA high time tCLK + 5 ns tCLK + 5 ns tTAL 19-18 TA low time tCLK + 5 ns tCLK + 5 ns tTBH 19-18 TB high time tCLK + 5 ns tCLK + 5 ns tTBL 19-18 TB low time tCLK + 5 ns tCLK + 5 ns ICU/Development Input Signals tIs 19-24 Input setup time ISE, PFAIL, EXINTn Before RE CLK 15 ns 15 ns tIh 19-24 Input hold time ISE, PFAIL, EXINTn After RE CLK 0 0 Development Output Signals tPFSh 19-23 Output hold time PFS, PLI After RE CLK 0.5 * tCLK - 6 ns 0.5 * tCLK - 6 ns tPFSv 19-23 Output active/inactive time PFS, PLI After RE CLK 0.5 * tCLK + 12 ns 0.5 * tCLK + 12 ns Asynchronous Edge Detected Input Signals tasw 19-24 Input width EXINTn, HMEMRD, HMEMWR, ISE, KBSIN0-7, PFAIL PSCLK1-3, PSDAT1- 3 15 ns 15 ns Symbol Figure Description Reference Conditions VCC = 5 V 10% VCC = 3.3 V ± 10% Min Max Min Max |
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