PC87570 datasheet(138/168 Pages) NSC

138 / 168 page

138

Device Specifications

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19.4.2

Timing Tables

All output timings are guaranteed for 50 pF load, unless otherwise specified.

Table 19-9. Output Signals

Symbol Figure

Description

Reference

Conditions

VCC = 5 V 10%

VCC = 3.3 V ± 10%

Min

Max

Min

Max

RESET Input Signals

tEPLv

19-25 Valid time: External

pull-up and pull-down

resistors

Before end of 16th

clock cycle of CLK

6 * tCLK

tIRST

19-25 Internal power-on

reset time

Power stable to end

of 16th clock cycle of

CLK

16 * tCLK + 30

ms + t32KW

16 * tCLK + 30

16 * tCLK +

30 ms +

t32KW

tSUPUP

19-25 Supply wake-up time

to 95% VCC

After VCC > VCCON

1 ms

tWRST

19-26 HMR width

HMR RE to HMR FE

3 * tCLK

tRSTia

19-26 HMR inactive

After HMR FE

tCLK + 5 ns

RESET Output Signals

tIPLv

19-25 Valid time: Internal

pull-up and pull-down

resistors

Before end of 16th

clock cycle of CLK

16 * tCLK

Clock Input Signal

t32KCLKIN 19-5 Required clock period

for 32KCLKIN. See

Section 6-2 on

page 65.

From RE to RE of

32KCLKIN.

t32NOM =

30.517578

µs

30.5145

µs

(t32NOM -

100ppm)

30.5206

µs

(t32NOM -

100ppm)

30.5145

µs

(t32NOM -

100ppm)

30.5206

µs

(t32NOM -

100ppm)

Clock Output Signals

tCLK

19-6

CLK period

At 2.0V (both edges)

100 ns

250 ns

100 ns

250 ns

tCLKh

19-6

CLK high time

At 2.0V (both edges)

0.5 * tCLK -

5 ns

0.5 * tCLK -

5 ns

tCLKl

19-6

CLK low time

At 0.8V (both edges)

0.5 * tCLK -

5 ns

0.5 * tCLK -

5 ns

tCLKr

19-6

CLK rise time

0.8V to 2.0V

4 ns

6 ns

tCLKf

19-6

CLK fall time

2.0V to 0.8V

4 ns

6 ns

tCLKw

19-7

CLK wake-up time

From wake-up event

till CLK starts toggling

200

µs

200

µs

tCLKINTst 19-7 t

CLK period

Active mode in

steady state

0.99 *

tCLKINTnom

1.01 *

tCLKINTnom

0.99 *

tCLKINTnom

1.01 *

tCLKINTnom

tCLKINTwk 19-7 t

CLK period

After wake-up from

Idle

0.9 *

tCLKINTnom

1.1 *

tCLKINTnom

0.9 *

tCLKINTnom

1.1 *

tCLKINTnom

tCLKstab

19-7

tCLK stabilization time After wake-up from

Idle

0.5 sec

t32KW

19-5

32K oscillator

wake-up time

After VBAT>VLOWBAT

1 sec

t32KD

19-6

CLK delay time

After VCC>VCCON

40 ms

BIU Input Signals

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