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L4984D

THD optimizer circuit

Figure 36. HD optimization: standard PFC controller

Figure 35

shows the internal block diagram of the THD optimizer circuit.

To take maximum benefit from the THD optimizer circuit, the high-frequency filter capacitor

after the bridge rectifier should be minimized, compatibly with EMI filtering needs. A large

capacitance, in fact, introduces a conduction dead-angle of the AC input current - even with

an ideal energy transfer by the PFC pre-regulator - therefore reducing the effectiveness of

the optimizer circuit.

Essentially, the circuit artificially increases the on-time of the power switch with a positive

offset added to the output of the multiplier in the proximity of the line voltage zero-crossings.

This offset is reduced as the instantaneous line voltage increases, so that it becomes

negligible as the line voltage moves toward the top of the sinusoid. Furthermore, the offset is

modulated by the voltage on the VFF pin (see Section 8: Voltage feedforward) so as to have

little offset at low line, where energy transfer at zero-crossings is typically quite good, and a

larger offset at high line where the energy transfer gets worse.

The effect of the circuit is shown in Figure 36, where the key waveforms of a standard PFC

controller are compared to those of this chip. Note the significant reduction in the region

around the zero-crossing where the drain voltage cannot reach the output voltage and how

switching frequency drops dramatically near the zero-crossing.