STIPN2M50-H datasheet(15/21 Pages) STMICROELECTRONICS

15 / 21 page

STIPN2M50-H

Application circuit example

DocID030065 Rev 4

15/21

5.1

Guidelines



Input signals HIN, LIN are active high logic. A 375 kΩ (typ.) pull-down resistor is built-

in for each input. To prevent the input signal oscillation, the wiring of each input should

be as short as possible and the use of RC filters (R1, C1) on each input signal is

suggested. The filters should be with a time constant of about 100 ns and placed as

close as possible to the IPM input pins.



The use of a bypass capacitor CVCC (aluminum or tantalum) can help to reduce the

transient circuit demand on the power supply. Besides, to reduce high frequency

switching noise distributed on the power lines, a decoupling capacitor C2 (100 to 220

nF, with low ESR and low ESL) should be placed as close as possible to Vcc pin and in

parallel with the bypass capacitor.



The use of RC filter (RSF, CSF) is recommended to avoid protection circuit

malfunction. The time constant (RSF x CSF) should be set to 1 μs and the filter must

be placed as close as possible to CIN pin.



The

̅̅̅̅ is an input/output pin (open-drain type if it is used as output). The CSD

capacitor of the filter on

̅̅̅̅ should be fixed no higher than 3.3 nF in order to ensure

the

̅̅̅̅ activation time Ƭ

≤ 500 ns; the filter should be placed as close as possible to

the

̅̅̅̅ pin.



The decoupling capacitor C3 (from 100 to 220 nF, ceramic with low ESR and low

ESL), in parallel with each Cboot, is useful to filter high frequency disturbance. Both

Cboot and C3 (if present) should be placed as close as possible to the U, V, W and Vboot

pins. Bootstrap negative electrodes should be connected to U, V, W terminals directly

and separated from the main output wires.



To prevent the overvoltage on Vcc pin, a Zener diode (Dz1) can be used. Similarly on

the Vboot pin, a Zener diode (Dz2) can be placed in parallel with each Cboot.



The use of the decoupling capacitor C4 (100 to 220 nF, with low ESR and low ESL) in

parallel with the electrolytic capacitor Cvdc is useful to prevent surge destruction. Both

capacitors C4 and Cvdc should be placed as close as possible to the IPM (C4 has

priority over Cvdc).



By integrating an application-specific type HVIC inside the module, coupling to the

MCU terminals without an optocoupler is possible.



Low inductance shunt resistors should be used for phase leg current sensing.



In order to avoid malfunctions, the wiring on N pins, the shunt resistor and PWR_GND

should be as short as possible.



The connection of SGN_GND to PWR_GND on one point only (close to the shunt

resistor terminal) can help to reduce the impact of power ground fluctuation.

These guidelines ensure the specifications of the device for application designs. For further

details, please refer to the relevant application note.

Table 15: Recommended operating conditions

Symbol

Parameter

Test conditions

Min.

Typ.

Max.

Unit

VPN

Supply voltage

Applied among P-Nu, Nv,

300

400

VCC

Control supply voltage

Applied to VCC-GND

13.5

VBS

High-side bias voltage

Applied to VBOOTi-OUTi for

i = U, V, W

tdead

Blanking time to prevent arm-

short

For each input signal

µs

fPWM

PWM input signal

-40 °C < Tc < 100 °C

-40 °C < Tj < 125 °C

kHz

Case operation temperature

100

°C

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