PC87309VLJ datasheet(139/192 Pages) NSC

139 / 192 page

Enhanced Serial Port - UART1 (Logical Device 3)

139

www.national.com

Bits 7-0 - Transmitted Data

Used to access the Transmitter Holding Register when

the FIFOs are disabled or the top of TX_FIFO when the

FIFOs are enabled.

6.5.2

Interrupt Enable Register (IER)

This register controls the enabling of various interrupts.

Some interrupts are common to all operating modes of the

module, while others are mode specific. Bits 4 to 7 can be

set in Extended mode only. They are cleared in Non-Ex-

tended mode. The bits of the Interrupt Enable Register

(IER) are defined differently, depending on operating the

module in Extended or Non-Extended mode.

The following sections describe the bits in this register for

each of these modes.

The reset mode for the IER is the Non-Extended UART

mode.

When edge-sensitive interrupt triggers are employed, user is

advised to clear all IER bits immediately upon entering the in-

terrupt service routine and to re-enable them prior to exiting

(or alternatively, to disable CPU interrupts and re-enable pri-

or to exiting). This will guarantee proper interrupt triggering in

the interrupt controller in case one or more interrupt events

occur during execution of the interrupt routine.

If the LSR, MSR or EIR registers are to be polled, interrupt

sources which are identified by self-clearing bits should

have their corresponding IER bits set to 0, to prevent spuri-

ous pulses on the interrupt output pin.

If an interrupt source must be disabled, the CPU can do so

by clearing the corresponding bit in the IER register. How-

ever, if an interrupt event occurs just before the correspond-

ing enable bit in the IER register is cleared, a spurious

interrupt may be generated. To avoid this problem, the

clearing of any IER bit should be done during execution of

the interrupt service routine. If the interrupt controller is pro-

grammed for level-sensitive interrupts, the clearing of IER

bits can also be performed outside the interrupt service rou-

tine, but with the CPU interrupt disabled.

Interrupt Enable Register (IER), in the Non-Extended

Mode

Upon reset, the IER supports the Non-Extended mode. See

the bitmap of the Interrupt Enable Register in these modes.

Bit 0 - Receiver High-Data-Level Interrupt Enable

(RXHDL_IE)

Setting this bit enables interrupts on Receiver High-

Data-Level, or RX_FIFO Time-Out events (EIR Bits 3-0

are 0100 or 1100. See Table 6-3 on page 141).

0: Disable Receiver High-Data-Level and RX_FIFO

Time-Out interrupts (Default).

1: Enable Receiver High-Data-Level and RX_FIFO

Time-Out interrupts.

Bit 1 - Transmitter Low-Data-Level Interrupt Enable

(TXLDL_IE)

Setting this bit enables interrupts on Transmitter Low

Data-Level-events (EIR Bits 3-0 are 0010. See Table

6-3 on page 141).

0: Disable Transmitter Low-Data-Level Interrupts (De-

fault).

1: Enable Transmitter Low-Data-Level Interrupts.

Bit 2 - Line Status Interrupt Enable (LS_IE)

Setting this bit enables interrupts on Line Status events.

(EIR Bits 3-0 are 0110. See Table 6-3 on page 141).

0: Disable Line Status Interrupts (LS_EV) (Default).

1: Enable Line Status Interrupts (LS_EV).

Bit 3 - Modem Status Interrupt Enable (MS_IE)

Setting this bit enables the interrupts on Modem Status

events. (EIR Bits 3-0 are 0000. See Table 6-3 on page

141).

0 - Disable Modem Status Interrupts (MS_EV) (De-

fault).

1: Enable Modem Status Interrupts (MS_EV).

Bits 7-4- Reserved

These bits are reserved.

76543210

Reset

Required

Transmitter Data

Port (TXD)

Bank 0,

Transmitted Data

Offset 00h

76543210

Reset

Required

MS_IE

Reserved

Interrupt Enable

RXHDL_IE

TXLDL_IE

LS_IE

Bank 0,

IER in Non-Extended Modes

Offset 01h

Reserved

PC87309VLJ датащи(PDF) 139 Page - National Semiconductor (TI)

PC87309VLJ датащи(HTML) 139 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL