PC87309VLJ datasheet(137/192 Pages) NSC

137 / 192 page

Enhanced Serial Port - UART1 (Logical Device 3)

137

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6.2.1

16450 or 16550 UART Mode

The module defaults to 16450 mode after power up or reset.

UART 16550 mode is equivalent to 16450 mode, with the

addition of a 16-byte data FIFO for more efficient data I/O.

Transparent compatibility is maintained with this UART

mode in this module.

Despite the many additions to the basic UART hardware

and organization, the UART responds correctly to existing

software drivers with no software modification required.

When 16450 software initializes and addresses this mod-

ule, it will in always perform as a 16450 device.

Data transfer takes place by use of data buffers that inter-

face internally in parallel and with the external data channel

in a serial format. 16-byte data FIFOs may reduce host

overhead by enabling multiple-byte data transfers within a

single interrupt. With FIFOs disabled, this module is equiv-

alent to the standard 16450 UART. With FIFOs enabled, the

hardware functions as a standard 16550 UART.

The composite serial data stream interfaces with the data

channel through signal conditioning circuitry such as

TTL/RS232 converters, modem tone generators, etc.

Data transfer is accompanied by software-generated con-

trol signals, which may be utilized to activate the communi-

cations channel and “handshake” with the remote device.

These may be supplied directly by the UART, or generated

by control interface circuits such as telephone dialing and

answering circuits, etc.

FIGURE 6-2. Composite Serial Data

The composite serial data stream produced by the UART is

illustrated in Figure 6-2. A data word containing five to eight

bits is preceded by start bits and followed by an optional

parity bit and a stop bit. The data is clocked out, LSB first,

at a predetermined rate (the baud).

The data word length, parity bit option, number of start bits

and baud rate are programmable parameters.

The UART includes a programmable baud rate generator

that produces the baud rate clocks and associated timing

signals for serial communication.

The system can monitor this module status at any time. Sta-

tus information includes the type and condition of the trans-

fer operation in process, as well as any error conditions

(e.g., parity, overrun, framing, or break interrupt).

The module resources include modem control capability

and a prioritized interrupt system. Interrupts can be pro-

grammed to match system requirements, minimizing the

CPU overhead required to handle the communications

Line.

Programmable Baud Generator

This module contains a programmable baud rate generator

that generates the clock rates for serial data communication

(both transmit and receive channels). It divides its input

clock by any divisor value from 1 to 216 - 1. The output clock

frequency of the baud rate generator must be programmed

to be sixteen times the baud rate value. A 24 MHz input fre-

quency is divided by a prescale value (PRESL field of

EXCR2 - see page 149. Its default value is 13) and by a 16-

bit programmable divisor value contained in the Baud Gen-

erator Divisor High and Low registers (BGD(H) and BGD(L)

- see page 148). Each divisor value yields a clock signal

(BOUT) and a further division by 16 produces the baud rate

clock for the serial data stream. It may also be output as a

test signal when enabled (see bit 7 of EXCR1 on page 149.)

These user-selectable parameters enable the user to gen-

erate a large choice of serial data rates, including all stan-

dard baud rates. A list of baud rates and their settings

appears in Table 6-12 on page 148.

Module Operation

Before module operation can begin, both the communica-

tions format and baud rate must be programmed by the soft-

ware. The communications format is programmed by

loading a control byte into the LCR register, while the baud

rate is selected by loading an appropriate value into the

baud rate generator divisor registers and the divisor prese-

lect values (PRESL) into EXCR2 (see page 149).

The software can read the status of the module at any time

during operation. The status information includes full or

empty state for both transmission and reception channels,

and any other condition detected on the received data

stream, like parity error, framing error, data overrun, or

break event.

6.2.2

Extended UART Mode

In Extended UART mode of operation, the module configu-

ration changes and additional features become available

which enhance UART capabilities.

The interrupt sources are no longer prioritized; they

are presented bit-by-bit in the EIR (see page 140).

An auxiliary status and control register replaces the

scratchpad register. It contains additional status and

control ﬂag bits (“Auxiliary Status and Control Register

(ASCR)” on page 146).

The TX_FIFO can generate interrupts when the num-

ber of outgoing bytes in the TX_FIFO drops below a

programmable threshold. In the Non-Extended UART

modes, only reception FIFOs have the thresholding

feature.

6.3

FIFO TIME-OUTS

Time-out mechanisms prevent received data from remain-

ing in the RX_FIFO indefinitely, if the programmed interrupt

threshold is not reached.

An RX_FIFO time-out generates a Receiver Data Ready in-

terrupt if bit 0 of IER is set to 1. An RX_FIFO time-out also

sets bit 0 of ASCR to 1 if the RX_FIFO is below the thresh-

old. When a Receiver Data Ready interrupt occurs, this bit

is tested by the software to determine whether a number of

bytes indicated by the RX_FIFO threshold can be read with-

out checking bit 0 of the LSR register.

The conditions that must exist for a time-out to occur in the

various modes of operation are described below.

When a time-out has occurred, it can only be reset when the

FIFO is read by the CPU.

Time-out event A generates an interrupt and sets the

RXF_TOUT bit (bit 0 of ASCR) when all of the following are

true:

At least one byte is in the RX_FIFO, and

More than 64

µsec or four character times, whichever is

greater, have elapsed since the last byte was loaded

into the RX_FIFO from the receiver logic, and

START -LSB- DATA 5-8 -MSB- PARITY

STOP

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