PC87309VLJ datasheet(130/192 Pages) NSC

130 / 192 page

Enhanced Serial Port with IR -UART2 (Logical Device 2)

130

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Bits 2-0 - Consumer-IR Mode Transceiver Conﬁguration,

Low-Speed (RCLC)

These bits drive the ID/IRSL(2-0) pins when AMCFG is

1 and Consumer-IR mode with 30-56 KHz receiver car-

rier frequency is selected. They are unused when AM-

CFG

when

the

ID/IRSL(2-0)

pins

are

programmed as inputs. Upon read, these bits return the

values previously written.

Bit 3 - Reserved

Read/Write 0.

Bits 6-4 - Consumer-IR Mode Transceiver Conﬁguration,

High-Speed (RCHC)

These bits drive the IRSL(2-0) pins when AMCFG (bit 7

of IRCFG4) is 1 and Consumer-IR mode with 400-480

KHz receiver carrier frequency is selected. They are un-

used when AMCFG is 0 or when the ID/IRSL(2-0) pins

are programmed as inputs.

Upon read, these bits return the values previously writ-

ten.

Bit 7 - Reserved

Read/Write 0.

5.18.8

Infrared Interface Configuration Register 4

(IRCFG4)

This register configures the receiver data path and enables

the automatic selection of the configuration pins.

After reset, this register contains 00h.

Bits 2-0 - Reserved

Read/write 0.

Bit 3- ID/IRSL(2-1) Pins’ Direction Select (IRSL21_DS)

This bit determines the direction of the ID/IRSL2 and

ID/IRSL1 pins.

0: Pins’ direction is input.

1: Pins’ direction is output.

Bit 4 - IRRX Signal Invert (RXINV)

This bit supports optical transceivers with receive sig-

nals of opposite polarity (active high instead of active

low).

When set to 1 an inverter is put on the path of the input

signal of the receiver.

Bit 5 - ID0/IRSL0/IRRX2 Pin Direction Select (IRSL0_DS)

This

bit

determines

the

direction

the

ID0/

IRSL0/IRRX2 pin. See Table 5-29 on page 130.

0: Pin’s direction is input.

1: Pin’s direction is output.

Bit 6 - Reserved

Read/Write 0.

Bit 7 - Automatic Module Conﬁguration (AMCFG)

When set to 1, this bit enables automatic infrared con-

figuration.

TABLE 5-29. Infrared Receiver Input Selection

1. IRCFG4 is in bank 7, offset 07h. It is

described on page 130.

2. AUX_IRRX (bit 4 of IRCR2) is described on

page 124.

76543210

Reset

Required

Infrared Configuration

(IRCFG4)

Bank 7,

Reserved

RXINV

IRSL0_DS

Reserved

AMCFG

Reserved

IRSL21_DS

Offset 07h

Bit 5 of IRCFG41

(IRSL0_DS)

Bit 4 of IRCR2

(AUX_IRRX)2

Selected IRRX

IRRX1

IRRX2

IRRX1

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