PC87309VLJ datasheet(129/192 Pages) NSC

129 / 192 page

Enhanced Serial Port with IR -UART2 (Logical Device 2)

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1: Oversampling mode.

Bit 7 - Run Length Control (R_LEN)

Enables or disables run length encoding/decoding. The

format of a run length code is:

YXXXXXXX

where, Y is the bit value and XXXXXXX is the number

of bits minus 1 (Selects from 1 to 128 bits).

0: Run Length Encoding/decoding is disabled.

1: Run Length Encoding/decoding is enabled.

5.18.4

Link Control/Bank Select Registers (LCR/BSR)

These registers are the same as the registers at offset

03h in bank 0.

5.18.5

Infrared Interface Configuration Register 1

(IRCFG1)

This register holds the transceiver configuration data for

Sharp-IR and SIR modes. It is also used to directly control

the transceiver operation mode when automatic configura-

tion is not enabled. The four least significant bits are also

used to read the identification data of a Plug and Play infra-

red interface adaptor.

Bit 0 - Transceiver Identiﬁcation/Control Bit 0 (IRIC0)

The function of this bit depends on whether the

ID0/IRSL0/IRRX2 pin is programmed as an input or an

output.

If ID0/IRSL0/IRRX2 is programmed as an input

(IRSL0_DS = 0) then:

— Upon read, this bit returns the logic level of the pin

(allowing external devices to identify themselves).

— Data written to this bit position is ignored.

If ID0/IRSL0/IRXX2 is programmed as an output

(IRSL0_DS = 1), then:

— If AMCFG (bit 7 of IRCFG4) is set to 1, this bit drives

the ID0/IRSL0/IRRX2 pin when Sharp-IR mode is

selected.

— If

AMCFG

this

bit

will

drive

the

ID0/IRSL0/IRRX2 pin, regardless of the selected

mode.

Upon read, this bit returns the value previously written.

Bits 2-1 - Transceiver Identiﬁcation/Control Bits 2-1 (IRIC2-

The function of these bits depends on whether the

ID/IRSL(2-1) pins are programmed as inputs or outputs.

If ID/IRSL(2-1) are programmed as input (IRSL21_DS =

0) then:

— Upon read, these bits return the logic level of the

pins (allowing external devices to identify them-

selves).

— Data written to these bit positions will be ignored.

If ID/IRSL(2-1) are programmed as output (IRSL21_DS

= 1) then:

— If AMCFG (bit 7 of IRCFG4) is set to 1, these bits

drive the ID/IRSL(2-1) pins when Sharp-IR mode is

selected.

— If AMCFG is 0, these bits will drive the ID/IRSL(2-

1)pins, regardless of the selected mode.

Upon read, these bits return the values previously written.

Bit 3 - Transceiver identiﬁcation (IRID3)

Upon read, this bit returns the logic level of the ID3 pin.

Data written to this bit position is ignored.

Bits 6-4 - SIR Mode Transceiver Conﬁguration (SIRC(2-0))

These bits will drive the ID/IRSL(2-0) pins when AMCFG

(bit 7 of IRCFG4) is 1 and SIR mode is selected. They

are unused when AMCFG is 0 or when the ID/IRSL (2-

0) pins are programmed as inputs. SIRC0 is also un-

used when the IRSL0_DS bit in IRCFG4 is 0.

Upon read, these bits return the values previously written.

Bit 7 - Special Transceiver Mode Selection (STRV_MS)

When this bit is set to 1, the IRTX output signal is forced

to active high and a timer is started.

The timer times out after 64

µsec, at which time the bit

is reset and the IRTX output signal becomes low again.

The timer is restarted every time a 1 is written to this bit.

Although it is possible to extend the period during which

IRTX remains high beyond 64

µsec, this should be

avoided to prevent damage to the transmitter LED.

Writing a zero to this bit has no effect.

5.18.6

Reserved Register

Bank 7 register with offset 05h is reserved.

5.18.7

Infrared Interface Configuration 3 Register

(IRCFG3)

This register sets the external transceiver configuration for

the low speed and high speed Consumer IR modes of op-

eration. Upon reset, the content of this register is 00h.

76543210

Reset

Required

Infrared Configuration

(IRCFG1)

Bank 7,

IRIC(2-0)

SIRC(2-0)

IRID3

STRV_MS

Offset 04h

76543210

Reset

Required

Infrared Configuration

(IRCFG3)

Bank 7,

RCLC(2-0)

RCHC(2-0)

Reserved

Offset 06h

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