PC87309VLJ datasheet(114/192 Pages) NSC

114 / 192 page

Enhanced Serial Port with IR -UART2 (Logical Device 2)

114

www.national.com

TABLE 5-9. Bank Selection Encoding

5.11.7

Modem/Mode Control Register (MCR)

This register controls the interface with the modem or data

communications set, and the device operational mode

when the device is in the Extended mode. The register

function differs for Extended and Non-Extended modes.

Modem/Mode Control Register (MCR), Non-Extended

Mode

Bit 0 - Data Terminal Ready (DTR)

This bit controls the DTR signal output. When set to 1,

DTR is driven low. When loopback is enabled (LOOP is

set to 1), this bit internally drives DSR.

Bit 1 - Request To Send (RTS)

This bit controls the RTS signal output. When set to 1,

drives RTS low. When loopback is enabled (LOOP is

set), this bit drives CTS, internally.

Bit 2 - Loopback Interrupt Request (RILP)

When loopback is enabled, this bit internally drives RI.

Otherwise it is unused.

Bit 3 - Interrupt Signal Enable (ISEN) or Loopback DCD

(DCDLP)

In normal operation (standard 16450 or 16550) mode,

this bit controls the interrupt signal and must be set to 1

in order to enable the interrupt request signal.

When loopback is enabled, the interrupt output signal is

always enabled, and this bit internally drives DCD.

New programs should always keep this bit set to 1 dur-

ing normal operation. The interrupt signal should be

controlled through the Plug-n-Play logic.

Bit 4 - Loopback Enable (LOOP)

When this bit is set to 1, it enables loopback. This bit ac-

cesses the same internal register as bit 4 of the EXCR1

120 for more information on the Loopback mode).

0: Loopback disabled. (Default)

1: Loopback enabled.

Bits 7-5 - Reserved

Read/Write 0.

Modem/Mode Control Register (MCR), Extended Mode

In Extended mode, this register is used to select the opera-

tion mode (IrDA, Sharp, etc.) of the device and to enable the

DMA interface. In these modes, the interrupt output signal

is always enabled, and loopback can be enabled by setting

bit 4 of the EXCR1 register.

Bit 0 - Data Terminal Ready (DTR)

This bit controls the DTR signal output. When set to1,

DTR is driven low. When loopback is enabled (LOOP is

set), this bit internally drives both DSR and RI.

Bit 1 - Request To Send (RTS)

This bit controls the RTS signal output. When set to1,

RTS is driven low. When loopback is enabled (LOOP is

set), this bit internally drives both CTS and DCD.

Bit 2 - DMA Enable (DMA_EN)

When set to1, DMA mode of operation is enabled. When

DMA is selected, transmit and/or receive interrupts

should be disabled to avoid spurious interrupts.

DMA cycles always address the Data Holding Registers

or FIFOs, regardless of the selected bank.

BSR Bits

Bank

Selected

LCR

76543210

LCR is

written

xxxxxx

xxxx

xxxxx

LCR is not

written

11100100

11101000

11101100

11110000

11110100

Reserved

76543210

Reset

Required

Modem Control

Bank 0,

Non-Extended UART mode

RILP

LOOP

Reserved

DTR

RTS

ISEN or DCDLP

Offset 04h

76543210

Reset

Required

Modem Control

Bank 0,

Extended Mode

DMA_EN

Reserved

MDSL0

MDSL1

MDSL2

DTR

RTS

TX_DFR

Offset 04h

PC87309VLJ датащи(PDF) 114 Page - National Semiconductor (TI)

PC87309VLJ датащи(HTML) 114 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL