PC87309VLJ datasheet(110/192 Pages) NSC

110 / 192 page

Enhanced Serial Port with IR -UART2 (Logical Device 2)

110

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Bit 2 - Link Status Interrupt Enable (LS_IE) or TX_FIFO

Underrun Interrupt Enable (TXUR_IE)

On reception, Setting this bit enables Link Status Interrupts.

On transmission, Setting this bit enables TX_FIFO un-

derrun interrupts.

0: Disable Link Status and TX_FIFO underrun inter-

rupts (Default)

1: Enable Link Status and TX_FIFO underrun interrupts.

Bit 7-3 - Same as in the Extended Modes of UART and

Sharp-IR (See the section “Interrupt Enable Register (IER),

in the Extended Modes of UART, Sharp-IR and SIR” on

page 109).

5.11.3

Event Identification Register (EIR)

The Event Identification Register (EIR) and the FIFO

Control Register (FCR) (see next register description)

share the same address. The EIR is accessed during CPU

read cycles while the FCR is accessed during CPU write cy-

cles.The Event Identification Register (EIR) indicates the in-

terrupt source. The function of this register changes

according to the selected mode of operation.

Event Identiﬁcation Register (EIR), Non-Extended Mode

When Extended mode is not selected (EXT_SL bit in

EXCR1 register is set to 0), this register is the same as in

the 16550.

In a Non-Extended UART mode, this module prioritizes in-

terrupts into four levels. The EIR indicates the highest level

of interrupt that is pending. The encoding of these interrupts

is shown in Table 5-3 on page 110.

Bit 0 - Interrupt Pending Flag (IPF)

0: There is an interrupt pending.

1: No interrupt pending. (Default)

Bits 2,1 - Interrupt Priority 1,0 (IPR1,0)

When bit 0 (IPF) is 0, these bits indicate the pending in-

terrupt with the highest priority. See Table 5-3 on page

110.

Default value is 00.

Bit 3 - RX_FIFO Time-Out (RXFT)

In the 16450 mode, this bit is always 0. In the 16550

mode (FIFOs enabled), this bit is set to 1 when an

RX_FIFO read time-out occurred and the associated in-

terrupt is currently the highest priority pending interrupt.

Bits 5,4 - Reserved

Read/Write 0.

Bit 7,6 - FIFOs Enabled (FEN1,0)

0: No FIFO enabled. (Default)

1: FIFOs are enabled (bit 0 of FCR is set to 1).

TABLE 5-3. Non-Extended Mode Interrupt Priorities

76543210

Reset

Required

Non-Extended Modes, Read Cycles

IPR1 - Interrupt Priority 1

Reserved

FEN0 - FIFOs Enabled

FEN1 - FIFOs Enabled

Event Identification

IPF - Interrupt Pending

IPR0 - Interrupt Priority 0

RXFT - RX_FIFO Time-Out

Bank 0,

Offset 02h

EIR Bits

3 2 1 0

Interrupt Set and Reset Functions

Priority

Level

Interrupt Type

Interrupt Source

Interrupt Reset Control

0 0 0 1

−

None

−

0 1 1 0

Highest

Link Status

Parity error, framing error, data overrun

or break event

Read Link Status Register (LSR).

0 1 0 0

Second

Receiver High

Data Level

Event

Receiver Holding Register (RXD) full, or

RX_FIFO level equal to or above

threshold.

Reading the RXD or, RX_FIFO level

drops below threshold.

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