PC87309VLJ datasheet(112/192 Pages) NSC

112 / 192 page

Enhanced Serial Port with IR -UART2 (Logical Device 2)

112

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5.11.4

FIFO Control Register (FCR)

The FIFO Control Register (FCR) is write only. It is used to

enable the FIFOs, clear the FIFOs and set the interrupt

thresholds levels for the reception and transmission FIFOs.

Bit 0 - FIFO Enable (FIFO_EN)

When set to 1 enables both the Transmision and Recep-

tion FIFOs. Resetting this bit clears both FIFOs.

In Consumer-IR modes the FIFOs are always enabled

and the setting of this bit is ignored.

Bit 1 - Receiver Soft Reset (RXSR)

Writing a 1 to this bit generates a receiver soft reset,

which clears the RX_FIFO and the receiver logic. This

bit is automatically cleared by the hardware.

Bit 2 - Transmitter Soft Reset (TXSR)

Writing a 1 to this bit generates a transmitter soft reset,

which clears the TX_FIFO and the transmitter logic. This

bit is automatically cleared by the hardware.

Bit 3 - Reserved

Read/Write 0.

Writing to this bit has no effect on the UART operation.

Bits 5,4 - TX_FIFO Threshold Level (TXFTH1,0)

These bits select the TX_FIFO interrupt threshold level.

An interrupt is generated when the level of the data in

the TX_FIFO drops below the encoded threshold.

TABLE 5-5. TX_FIFO Level Selection

Bits 7,6 - RX_FIFO Threshold Level (RXFTH1,0)

These bits select the RX_FIFO interrupt threshold level.

An interrupt is generated when the level of the data in

the RX_FIFO is equal to or above the encoded thresh-

old.

TABLE 5-6. RX_FIFO Level Selection

5.11.5

Link Control Register (LCR) and Bank

Selection Register (BSR)

The Link Control Register (LCR) and the Bank Select

dress.

The Link Control Register (LCR) selects the communica-

tions format for data transfers in UART, SIR and Sharp-IR

modes.

Upon reset, all bits are set to 0.

Reading the register at this address location returns the

content of the BSR. The content of LCR may be read from

the Shadow of Link Control Register (SH_LCR) register in

bank 3 (See Section 5.14.2 on page 122). During a write op-

eration to this register at this address location, the setting of

bit 7 (Bank Select Enable, BKSE) determines whether LCR

or BSR is to be accessed, as follows:

If bit 7 is 0, the write affects both LCR and BSR.

If bit 7 is 1, the write affects only BSR, and LCR remains

unchanged. This prevents the communications format

from being spuriously affected when a bank other than

0 or 1 is accessed.

Upon reset, all bits are set to 0.

Link Control Register (LCR)

Bits 6-0 are only effective in UART, Sharp-IR and SIR

modes. They are ignored in Consumer-IR mode.

Bits 1,0 - Character Length Select (WLS1,0)

These bits specify the number of data bits in each trans-

mitted or received serial character. Table 5-7 shows

how to encode these bits.

TXFTH (Bits 5,4) TX_FIF0 Threshold

00(Default)

76543210

Reset

Required

FIFO Control

Bank 0,

TXSR

TXFTH0

TXFTH1

RXFTH0

RXFTH1

FIFO_EN

RXSR

Reserved

Offset 02h

Write Cycles

RXFTH (Bits 5,4) RX_FIF0 Threshold

00(Default)

76543210

Reset

Required

Link Control

All Banks,

Offset 03h

STB

EPS

STKP

SBRK

BKSE

WLS0

WLS1

PEN

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