Function description

TDA7703

12/32

Rev 1

The sequence consists of the following phases:

●

START: SDA line transitioning from H to L with SCL fixed H. This signifies a new

transmission is starting;

●

data latching: on the rising SCL edge. The SDA line can transition only when SCL is

low (otherwise its transitions are interpreted as either a START or a STOP transition);

●

pulls it down if communication has been successful. Lack of the acknowledge pulse

generation from the TDA7703 means that the communication has failed;

●

a chip address byte must be sent at the beginning of the transmission. The value is C2

for "write";

●

as many data bytes as needed can follow the address before the communication is

terminated. See the next section for details on the frame format;

●

STOP: SDA line transitioning from L to H with SCL H. This signifies the end of the

transmission.

Red lines represent transmissions from the TDA7703 to the µP.

A "read" communication example is shown in the figure below, for an unspecified number of

data bytes (see later on for frame structure decription):

Figure 4.

The sequence is very similar to the "write" one and has the same constraints for start, stop,

data latching. The differences follow:

●

a chip address must always be sent by the µP to the TDA7703; the address must be

C3;

●

a header is transmitted after the chip address (the same happens for "write") before

data are transferred from the TDA7703 to the µP. See the Communication Protocol

Manual for details on the frame format;

●

when data are transmitted from the TDA7703 to the µP, the µP keeps the SDA line H;

●

the ACKnowledge pulse is generated by the µP for those data bytes that are sent by the

has the same effect on the TDA7703 as a STOP.

The max. clock speed is 500 kbit/s.

SDA

a7

a6

…

a0

d7

d6

…

d0

SCL

clk1

clk2

…

clk8

clk9

clk1

clk2

…

clk8

clk9

START

address

ACK

data

ACK

STOP