STM32F411RET6 datasheet(64/149 Pages) STMICROELECTRONICS

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Electrical characteristics

STM32F411xC STM32F411xE

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DocID026289 Rev 6

6.3.2

VCAP_1/VCAP_2 external capacitors

Stabilization for the main regulator is achieved by connecting the external capacitor CEXT to

the VCAP_1 and VCAP_2 pins. For packages supporting only 1 VCAP pin, the 2 CEXT

capacitors are replaced by a single capacitor.

CEXT is specified in Table 16.

Figure 19. External capacitor CEXT

1. Legend: ESR is the equivalent series resistance.

VDD = 2.4 to

2.7 V

Conversion

time up to

2.4 Msps

24 MHz

100 MHz with 4

wait states

– I/O

compensation

works

up to 50 MHz

16-bit erase

and program

operations

VDD = 2.7 to

3.6 V(6)

Conversion

time up to

2.4 Msps

30 MHz

100 MHz with 3

wait states

– I/O

compensation

works

–up to

100 MHz

when VDD =

3.0 to 3.6 V

–up to

50 MHz

when VDD =

2.7 to 3.0 V

32-bit erase

and program

operations

1. Applicable only when the code is executed from Flash memory. When the code is executed from RAM, no wait state is

required.

2. Thanks to the ART accelerator and the 128-bit Flash memory, the number of wait states given here does not impact the

execution speed from Flash memory since the ART accelerator allows to achieve a performance equivalent to 0 wait state

program execution.

3. Refer to Table 55: I/O AC characteristics for frequencies vs. external load.

4. VDD/VDDA minimum value of 1.7 V, with the use of an external power supply supervisor (refer to Section 3.15.2: Internal

reset OFF).

5. Prefetch is not available. Refer to AN3430 application note for details on how to adjust performance and power.

6. The voltage range for the USB full speed embedded PHY can drop down to 2.7 V. However the electrical characteristics of

D- and D+ pins will be degraded between 2.7 and 3 V.

Table 15. Features depending on the operating power supply range (continued)

Operating

power

supply

range

ADC

operation

Maximum

Flash

memory

access

frequency

with no wait

states

(fFlashmax)

Maximum Flash

memory access

frequency with

wait states (1)(2)

I/O operation

Clock output

frequency on

I/O pins(3)

Possible

Flash

memory

operations

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