LT5546

8

5546f

APPLICATIO S I FOR ATIO

To keep the DC resistance of L3 below 2

Ω, 120nH is used.

This disturbs the matching network slightly by causing the

frequency where the S11 is minimal to be lower than the

To compensate for this, the value of coupling capacitor C3

is lowered and will contribute some correcting reactance.

For low frequencies, it might not be possible to find any

practical inductor value for L3 with DC resistance smaller

than 2

Ω. In that case it is recommended to use a trans-

former with a center tap. The tolerance for the components

in Figure 1 can be 10% for a return loss higher than 16dB

and a gain reduction due to mismatch less than 0.3dB.

It is possible to simplify the input matching circuit and

compromise the performance. In Figure 2a, the simplified

matching network is given.

This matching network can deliver equal amplitudes to the

phase difference between the inputs will not be exactly 180

degrees. In practice, the phase shift will be around 145

Figure 1. Example L-C IF Input Matching Network at 280MHz

C3

56pF

C1

5.6pF

C2

5.6pF

L1

56nH

L3

120nH

L2

56nH

5546 F01

IF

INPUT

Table 1. The Component Values of Matching Network L1, L2, L3,

C1, C2 and C3.

L1, L2(nH)

C1, C2(pF)

L3(nH)

C3(pF)

50

340

34

1800

820

100

159

15.9

470

220

150

106

10.6

470

220

200

80

8.0

470

220

250

64

6.4

120

56

300

53

5.3

120

56

350

45

4.5

120

56

400

40

4.0

120

56

450

35

3.5

120

56

500

32

3.2

120

56

degrees, depending on the quality factor of the network.

This will result in a reduction in the gain. The higher the

chosen quality factor, the closer the phase difference will

approach 180 degrees. However, a higher quality factor

will reduce bandwidth and create more loss in the match-

ing network. For minimum board space, 0402 compo-

nents are used. The measured noise figure for maximum

gain with this matching network is about 9.4dB, and the

maximum gain is about 55dB. Assuming 0402 inductors

with Q = 35, the insertion loss of this network is about

2.5dB. The tolerance for the components in Figure 2a can

be 10% for a return loss higher than 10dB and a gain

reduction due to mismatch less than 0.5dB. The measured

input sensitivity for this matching network (see also Fig-

ure 11) is about –78.3dBm for a 10dB signal-to-noise

ratio.

For high gain settings, both the noise figure and the input

IP3 will be low. From a noise figure point of view, it is

advantageous to work as closely as possible to the maxi-

is increased beyond the maximum gain point (where

additional increase in control voltage does not give an

increase in gain), the response time of the gain control

circuit is increased. If control speed is crucial, a few dB of

gain margin should be allowed from the highest gain point

to be sure that at all temperatures, the maximum gain

setting is not crossed. At low gain settings, the noise figure

and the input IP3 will be high. Optionally, the control

nominal gain range from 1.6dB to 56.8dB. The linear-in-

control voltages as low as –0.35V. This results in an

Figure 2a. Simplified IF Input Matching Network at 280MHz

and Figure 2b. Simplified Circuit Schematic of the IF Inputs

75

Ω

C1

10pF

L1

15nH

L2

15nH

5546 F02

IF

INPUT

1mA

1mA

75

Ω

(2a)

(2b)