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STK6005 датащи(PDF) 26 Page - List of Unclassifed Manufacturers |
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STK6005 датащи(HTML) 26 Page - List of Unclassifed Manufacturers |
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26 / 36 page ![]() 26 STK6005 clear the interrupt flags and reset INTN output to high. 5.17 GPIO Ports STK6005 provides four general purpose inputs / outputs. These provide additional signals to control the various devices in the system. Each GPIO port can be independently programmed to input or output a direction (SelGPO) or a pulse width modulation output (SelPWM). 6. REGISTER DEFINITION 6.1 ADC Control Address Bit Name Initial R/W Description 0x10 [7:0] HBP[7:0] 0x28 R/W 0x11 [3:0] HBP[11:8] 0x1 R/W Horizontal back-porch length of input video, unit in number of input clocks 0x12 [7:0] HDISP[7:0] 0x00 R/W 0x13 [3:0] HDISP[11:8] 0x4 R/W Horizontal display active length of input video, unit in number of input clocks 0x14 [7:0] VBP[7:0] 0x23 R/W 0x15 [2:0] VBP[10:8] 0x0 R/W Vertical back-porch length of input video, unit in number of input scan lines 0x16 [7:0] VDISP[7:0] 0x00 R/W 0x17 [2:0] VDISP[10:8] 0x3 R/W Vertical display active length of input video, unit in number of input scan lines 0x18 [7:5] ClampSTA 0x2 R/W Clamp start from RGHS trailing edge ( # of RefCLKs) [4:0] ClampPW 0x08 R/W Clamp output pulse width ( # of RefCLKs) 0x19 [7:4] MaskBW 0x4 R/W Backward expansion width of VS mask (# of lines) [3:0] MaskFW 0x4 R/W Forward expansion width of VS mask (# of lines) 0x1A [5] EnClamp 0 R/W 0/1 : Clamp output low / enable [4] SetClamp 0 0/1 : to set Clamp output polarity to positive / negative [3] MaskSync 1 0/1 : MaskVS sync to RGHS leading / trailing edge [2] MaskExp 1 1 : enable MaskVS expansion [1] EnMaskVS 0 0/1 : MaskVS output low / enable [0] SetMask 0 0/1 : to set MaskVS output polarity to positive / negative 0x1B [6] SetICLK 0 R/W 0/1 : to set input clock polarity to positive / negative [5] SetIVS 0 0/1 : to set input Vsync polarity to positive / negative [4] SetIHS 0 0/1 : to set input Hsync polarity to positive / negative [3] HVMode 0 1 : VGAHS is composite sync and separates VS from it. [2] SelCSync 0 1 : to select Csync as Hsync / Vsync input [1] EnRGHS 1 0/1 : RGHS output low / enable [0] SetRGHS 0 0/1 : to set RGHS output polarity to positive / negative 0x1C [5] EnInter 0 R/W 1 : to enable a de-interlace function [4] L1Odd 1 1 : to indicate that Odd field is a first frame [3] HalfOdd 0 1 : VS active at half of HS period is an Odd field. [2] AdjEvenF 0 1 : to delay an active area of even field by 1 line [1] AdjOddF 0 1 : to delay an active area of odd field by 1 line [0] SelIntF 0 0/1 : YUV field is indicated by Field / HV sync timing. Back to Contents Table |
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