MP7529B

5

Rev. 2.00

DIGITAL INTERFACE

The digital inputs are designed to be both TTL and 5 V CMOS

compatible. All logic inputs are static protected MOS gates with

typical input currents of less than 10nA.

The control input DAC A/DAC B selects which DAC can ac-

cept data from the input port. Inputs CS and WR control the op-

erating mode of the selected DAC (

Table 1.). When CS and WR

are both low the selected DAC is in the write mode. The input

data latches of the selected DAC are transparent and its analog

output responds to activity on DB0-DB7 (Write mode). The se-

lected DAC latch retains the data which was present on

DB0-DB7 just prior to CS or WR assuming a high state. Both

analog outputs remain at the values corresponding to the data in

their respective latches (Hold mode).

VALID

CS

DAC A/

DAC B

WR

NOTE:

Figure 1. Write Cycle Timing Diagram

DB7-DB0

VALID

DAC A/

DAC B

CS

WR

DAC A

DAC B

L

H

X

X

L

L

H

X

L

L

X

H

WRITE

HOLD

HOLD

HOLD

HOLD

WRITE

HOLD

HOLD

L = Low State

H = High State

X = Don’t Care

Table 1. DAC’s Mode Selection

1.

MICROPROCESSOR INTERFACE

DAC A

DAC B

DB0

DB7

ADDRESS

DECODE

LOGIC

A0-A15

D0–D7

A+1***

A**

MP7529B*

CPU

6800

*Analog circuitry has been omitted for clarity

**A = Decoded 7529B DAC A Address

***A + 1 = Decoded 752B9 DAC B Address

Figure 2. MP7529B Dual DAC to 6800

CPU Interface

DAC A

DAC B

DB0

DB7

A8-A15

AD0–AD7

ADDRESS

DECODE

LOGIC

A+1***

A**

MP7529B*

CPU

8085

Figure 3. MP7529B Dual DAC to 8085

CPU Interface

LATCH

8212

ALE

NOTE:

8085 instruction shld (store H & L direct) can update

both DACS with data from H and L registers

*Analog circuitry has been omitted for clarity

**A = Decoded 7529B DAC A Address

***A + 1 = Decoded 7529B DAC B Address

Address Bus

Data Bus

Address Bus

ADDR/Data Bus

DAC A/DAC B

CS

WR

DAC A/DAC B

CS

WR

WR