PLL Functional Description

The simplified block diagram below shows the building blocks of frequency synthesizer and all internal registers, which are 20-bit

data register, 18-bit F-latch, 12-bit N-counter, and 6-bit R-counter.

The DATA stream is clocked into the data register on the rising edge of CLOCK signal, MSB first. The last two bits are the control

bits to indicate which register to be written. Upon the rising edge of the LE (Load Enable) signal, the rest of data bits is transferred

to the addressed register accordingly. The decoding scheme of the two control bits is as follows:

Control Bits

Register

C2

C1

0

0

N-Counter

1

0

R-Counter

X

1

F-Latch

Note: X = Don’t Care Condition

Programmable Feedback Divider (N-Counter)

The N-counter consists of the 6-bit swallow counter (A-counter) and the 6-bit programmable counter (B-counter). When the con-

trol bits are “00”, data is transferred from the 20-bit shift register into two 6-bit latches. One latch sets the A-counter while the other

sets the B-counter. The serial data format is shown below.

MSB

REGISTER’S BIT MAPPING

LSB

19

18

17

16

15

14

13

12

11

10

9

8

7

6

543210

RESERVED

N-COUNTER’s Divide Ratio

C2

C1

X

XXXXX

N12

N11

N10

N9

N8

N7

N6

N5

N4

N3

N2

N1

0

0

Note: X = Don’t Care Condition

Swallow Counter Divide Ratio (A-Counter)

Divide Ratio, A

N6

N5

N4

N3

N2

N1

0

000000

1

000001

*

******

63

111111

Note: Divide ratio must be from 0 to 63, and B must be

≥ A.

Programmable Counter Divide Ratio (B-Counter)

Divide Ratio, B

N12

N11

N10

N9

N8

N7

3

000

0

1

1

4

000

1

0

0

*

***

*

*

*

63

111

1

1

1

Note: Divide ratio must be from 3 to 63, and B must be

≥ A.

DS012815-4

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