Pin No.

Pin Name

I/O

Description

1V

CC

—

Power supply for CMOS section of PLL and ESD bussing.

2

MIXER

OUT

O

IF output from the mixer.

3V

CC

—

Power supply for mixer section.

4

GND

—

Ground.

5RF

IN

I

RF input to the mixer.

6

GND

—

Ground.

7Tx V

REG

—

Regulated power supply for external PA gain stage.

8V

CC

—

Power supply for analog sections of PLL and doubler.

9

GND

—

Ground.

10

Tx

OUT

O

Frequency doubler output.

11

GND

—

Ground.

12

V

CC

—

Power supply for analog sections of PLL and doubler.

13

GND

—

Ground.

14

GND

—

Ground.

15

f

IN

I

RF Input to PLL and frequency doubler.

16

CE

I

Chip Enable. Pulling LOW powers down entire chip. Taking CE HIGH powers up the

appropriate functional blocks depending on the state of bits F6, F7, F11, and F12

programmed in F-latch. It is necessary to initialize the internal registers once, after the

power up reset. The registers’ contents are kept even in power-down condition.

17

V

P

—

Power supply for charge pump.

18

D

o

O

Charge pump output. For connection to a loop filter for driving the input of an external VCO.

19

V

CC

—

Power supply for CMOS section of PLL and ESD bussing.

20

GND

—

Ground.

21

OUT 0

O

Programmable CMOS output. Refer to Function Register Programming Description section

for details.

22

Rx PD/OUT 1

I/O

Receiver power down control input or programmable CMOS output. Refer to Function

Register Programming Description section for details.

23

Tx PD/OUT 2

I/O

Transmitter power down control input or programmable CMOS output. Refer to Function

Register Programming Description section for details.

24

PLL PD

I

PLL power down control input. LOW for PLL normal operations, and HIGH for PLL power

saving.

25

CLOCK

I

26

DATA

I

MICROWIRE data input. High impedance CMOS input with Schmitt Trigger.

27

LE

I

MICROWIRE load enable input. High impedance CMOS input with Schmitt Trigger.

28

OSC

IN

I

Oscillator input. High impedance CMOS input with feedback.

29

S FIELD

I

DC compensation circuit enable. While LOW, the DC compensation circuit is enabled and

the threshold is updated through the DC compensation loop. While HIGH, the switch is

opened, and the comparator threshold is held by the external capacitor.

30

RSSI

OUT

O

Received signal strength indicator (RSSI) output.

31

THRESH

O

Threshold level to external comparator.

32

DC COMP

IN

I

Input to DC compensation circuit.

33

DISC

OUT

O

Demodulated output of discriminator.

34

GND

—

Ground.

35

V

CC

—

Power supply for the discriminator circuit.

36

QUAD

IN

I

Quadrature input for tank circuit.

37

V

CC

—

Power supply for limiter output stage.

38

GND

—

Ground.

39

V

CC

—

Power supply for limiter gain stages.

40

GND

—

Ground.

41

V

CC

—

Power supply for IF amplifier gain stages.

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