AD7779ACPZ datasheet(58/101 Pages) AD

58 / 101 page

Data Sheet

AD7779

Rev. A | Page 57 of 100

Minimum DCLKx Frequency

Select the DCLKx frequency ratio in such a way that the data is

completely shifted out before a new conversion is completed,

otherwise the previous conversion is overwritten and the trans-

mission becomes corrupt. The minimum DCLKx frequency ratio

is defined by the decimation rate, the operation mode, and the

lines enabled on the DOUT3 to DOUT0 data interface as

described in the following equations:

In standalone mode,

High Resolution Mode − DCLKMIN_RATIO < Decimation/

(8 × CHANNELS_PER_DOUT)

Low Power Mode − DCLKMIN_RATIO < Decimation/

(4 × CHANNELS_PER_DOUT)

In daisy-chain mode,

High Resolution Mode − DCLKMIN_RATIO< Decimation/

(8 × Devices × DOUTx Channels)

Low Power Mode − DCLKMIN_RATIO< Decimation/

(4 × Devices × DOUTx Channels)

As an example, when operating in master interface mode,

DOUTx = 01, the DOUT0 and DOUT1 pins shift out four Σ-Δ

channels each and, assuming a maximum output rate in high

resolution mode, the decimation = 128.

DCLKMIN < 128/ (8 × 4) = 4

If the DCLKMIN_RATIOis selected above the necessary minimum,

a Logic 0 is continuously transmitted until a new sample is

available.

An example in daisy-chain mode, assuming DOUTx = 01, and

with three devices connected and a decimation rate of 256 in

high resolution mode, is as follows:

DCLKMIN_RATIO < 256/(8 × 3 × 4) = 2.66 = 2

The different ratios are summarized in Table 38.

Table 38. Available DCLK Ratios

DCLK_CLK_DIV (SPI Control Mode),

DCLKx (Pin Control Mode)

DCLKx Ratio

000

001

010

011

100

101

110

111

128

There are maximum achievable ODRs and minimum DCLKx

frequencies required for a given DOUTx pin configuration, as

shown in Table 39 and Table 40.

Table 39. Maximum ODRs and Minimum DCLKx

Frequencies in High Resolution Mode

Decimation

Rate

ODR

(kSPS)

Minimum DCLKx (kHz)

1 DOUTx

2 DOUTx

4 DOUTx

4095

0.500122

128

2048

256

128

1024

512

256

128

512

1024

512

256

2048

1024

512

128

4096

2048

1024

Table 40. Maximum ODRs and Minimum DCLK

Frequencies in Low Power Mode

Decimation

Rate

ODR

(kSPS)

Minimum DCLK (kHz)

1 DOUT

2 DOUT

4 DOUT

2048

0.25

1024

0.5

128

512

256

128

256

512

256

128

1024

512

256

2048

1024

512

If the AD7779 operates in SPI control mode, it is possible to

adjust the DOUTx strength, which can be selected in the

DOUT_DRIVE_STR bits, as described in Table 41.

Table 41. DOUTx Strength

GENERAL_USER_CONFIG2, Bits[2:1]

Mode

Nominal

Strong

Weak

Extra strong

SPI Interface

The SPI interfaces gives the user flexibility to read the

conversion from the Σ-∆ ADC where the processor or

microcontroller is the master.

When a new conversion is completed, the DRDY signal is

toggled to indicate that data can be accessed. When DRDY

toggles, the internal channel counter is reset and the next SPI

read is from Channel 0 again. Conversely, after the last channel

data is read, all succeeding reads before the next DRDY signal

are from Channel 7 (LSB).

AD7779ACPZ датащи(PDF) 58 Page - Analog Devices

AD7779ACPZ датащи(HTML) 58 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL