LMC66 datasheet(17/24 Pages) NSC

17 / 24 page

6.0 Powerdown (Continued)

6.3 TEST CIRCUIT TO MEASURE t

ON AND tOFF

The circuit used to measure the t

ON, and tOFF during the

powerdown operation is a voltage follower with a load of

Ω as shown in Figure 14.

When the input to the powerdown pin is low, the LMC6681/

2/4 is on. Since the amplifier is connected in the voltage fol-

lower configuation, the output of the circuit is −1V. When the

powerdown pin is pulled high, the amplifier shuts down, and

draws less than 1 µA/Amplifier. In this powerdown mode, the

output pin has high impedance, and the output of the circuit

is pulled to 0V. t

ON is specified as the time between the 50%

points of the trailing edges of the input waveform at the pow-

erdown pin, and the waveform at the output pin. Similarly,

the t

OFF is specified as the time between the 50% points of

the leading edges of the input waveform at the powerdown

pin, and the waveform at the output pin.

6.4 t

ON and tOFF

The t

ON (time delay for device to power on) the tOFF (time de-

lay for device to power off) specs are guaranteed at a supply

voltage of 3V. The t

ON and tOFF spec are independent of the

PD applied in the specified range. Refer to the Powerdown

DC Threshold Characteristics table for the values for a logic

low and a logic high.

The guaranteed spec for t

ON is 200 µs. This does not mean

that the signal to the V

PD pin can be as high as 5 kHz (1/200

µs). Note that the V

PD frequency for the tON and tOFF mea-

surements is 5 Hz. The LMC6681/2/4 is ideal for DC type ap-

plications where the powerdown pin is controlled by low fre-

quency signals.

When the LMC6681/2/4 is powered off, internal bias currents

are shutoff. There is a inherent latency in the circuit, and the

device has to power off for a certain period of time for the t

spec to apply. Refer to the figure below. t

PD OFF refers to the

time interval for which the device is in the powerdown mode.

Consider the case when the device has been powered off for

5 ms, and then the powerdown pin is pulled to a logic low.

From

Figure 16, at room temperature, the device powers on

after 500 µs.

DS012042-16

FIGURE 14. Test Circuit for t

ON and tOFF Measurements

DS012042-17

(a) t

OFF Measurement

DS012042-29

(b) t

ON Measurement

FIGURE 15.

DS012042-39

FIGURE 16. t

ON Delay Till Active-On after

PDOFF in Powerdown Mode, VS = 3V

LMC66 датащи(PDF) 17 Page - National Semiconductor (TI)

LMC66 датащи(HTML) 17 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

датащи скачать

ссылки URL