WM8974 datasheet(48/63 Pages) WOLFSON

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WM8974

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PP Rev 1.1 September 2004

The PLL frequency ratio R = f2/f1 (see Figure 25) can be set using the register bits PLLK and PLLN:

PLLN = int R

PLLK = int (2

24 (R-PLLN))

EXAMPLE:

MCLK=12MHz, required clock = 12.288MHz.

R should be chosen to ensure 5 < PLLN < 13. There is a fixed divide by 4 in the PLL and a

selectable divide by N after the PLL which should be set to divide by 2 to meet this requirement.

Enabling the divide by 2 sets the required f2 = 4 x 2 x 12.288MHz = 98.304MHz.

R = 98.304 / 12 = 8.192

PLLN = int R = 8

k = int ( 2

24 x (8.192 – 8)) = 3221225 = 3126E9h

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

PLLPRESCALE

Divide MCLK by 2 before input to PLL

R36

PLL N value

3:0

PLLN

1000

Integer (N) part of PLL input/output

frequency ratio. Use values greater

than 5 and less than 13.

R37

PLL K value 1

5:0

PLLK [23:18]

0Ch

R38

PLL K Value 2

8:0

PLLK [17:9]

093h

R44

PLL K Value 3

8:0

PLLK [8:0]

0E9h

Fractional (K) part of PLL1

input/output frequency ratio (treat as

one 24-digit binary number).

Table 38 PLL Frequency Ratio Control

The PLL performs best when f2 is around 90MHz. Its stability peaks at N=8. Some example settings

are shown in Table 39.

MCLK

(MHz)

(F1)

DESIRED

OUTPUT

(MHz)

PRESCALE

DIVIDE

POSTSCALE

DIVIDE

(Hex)

11.29

90.3168

7.5264

86C227

12.288

98.304

8.192

3126E9

11.29

90.3168

6.947446

F28BD5

12.288

98.304

7.561846

8FD526

14.4

11.29

90.3168

6.272

45A1CB

14.4

12.288

98.304

6.826667

D3A06D

19.2

11.29

90.3168

2.352

5A1CAC

19.2

12.288

98.304

2.56

8F5C29

19.68

11.29

90.3168

2.294634

4B6D22

19.68

12.288

98.304

2.497561

7F6025

19.8

11.29

90.3168

2.280727

47DDBD

19.8

12.288

98.304

2.482424

7B802A

11.29

90.3168

1.8816

E1B08A

12.288

98.304

2.048

C49BA

11.29

90.3168

1.736862

BCA2F6

12.288

98.304

1.890462

E3F54B

11.29

90.3168

1.672533

AC2B23

12.288

98.304

1.820444

D208A5

19.8

11.29

90.3168

2.280727

47DDBD

19.8

12.288

98.304

2.482424

7B802A

Table 39 PLL Frequency Examples

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