REV. B

–6–

ADP3160/ADP3167

THEORY OF OPERATION

The ADP3160 and ADP3167 combine a current-mode, fixed

frequency PWM controller with antiphase logic outputs in a

controller for a 2-phase synchronous buck power converter.

Two-phase operation is important for switching the high currents

required by high-performance microprocessors. Handling the

high current in a single-phase converter would place difficult

requirements on the power components such as inductor wire

size, MOSFET ON resistance, and thermal dissipation. Their

high-side current sensing topology ensures that the load currents

are balanced in each phase, such that neither phase has to carry

more than half of the power. An additional benefit of high-side

current sensing over output current sensing is that the average

current through the sense resistor is reduced by the duty cycle

of the converter, allowing the use of a lower power, lower cost

resistor. The outputs of the ADP3160/ADP3167 are logic

drivers only and are not intended to drive external power

MOSFETs directly. Instead, the ADP3160/ADP3167 should

be paired with drivers such as the ADP3414 or ADP3417. A

system level block diagram of a 2-phase power supply for high

current CPUs is shown in Figure 5.

The frequency of the device is set by an external capacitor

connected to the CT pin. Each output phase operates at half of

the frequency set by the CT pin. The error amplifier and

current sense comparator control the duty cycle of the PWM

outputs to maintain regulation. The maximum duty cycle per

phase is inherently limited to 50% because the PWM outputs

toggle in 2-phase operation. While one phase is on, the other

phase is off. In no case can both outputs be high at the same time.

Output Voltage Sensing

The output voltage is sensed at the FB pin allowing for remote

sensing. To maintain the accuracy of the remote sensing, the

GND pin should also be connected close to the load. A voltage

voltage and a programmable reference voltage. The reference volt-

age is programmed between 1.1 V and 1.85 V by an internal 5-bit

DAC that reads the code at the voltage identification (VID) pins.

Refer to Table I for the output voltage versus VID pin code

information.

Active Voltage Positioning

The ADP3160 and ADP3167 use Analog Devices Optimal

Positioning Technology (ADOPT), a unique supplemental

regulation technique that uses active voltage positioning and

provides optimal compensation for load transients. When imple-

mented, ADOPT adjusts the output voltage as a function of the

load current, so that it is always optimally positioned for a load

transient. Standard (passive) voltage positioning has poor dynamic

performance, rendering it ineffective under the stringent repetitive

transient conditions required by high-performance processors.

ADOPT, however, provides optimal bandwidth for transient

response that yields optimal load transient response with the

minimum number of output capacitors.

Reference Output

A 3.0 V reference is available and is commonly used to set the

voltage positioning accurately using a resistor divider to the

COMP pin. In addition, the reference can be used for other

functions such as generating a regulated voltage with an external

amplifier. The reference is bypassed with a 1 nF capacitor to

ground. It is not intended to supply current to large capacitive

loads, and it should not be used to provide more than 1 mA of

output current.

Cycle-by-Cycle Operation

During normal operation (when the output voltage is regulated), the

voltage-error amplifier and the current comparator are the main

control elements. The voltage at the CT pin of the oscillator ramps

between 0 V and 3 V. When that voltage reaches 3 V, the oscillator

sets the driver logic, which sets PWM1 high. During the ON time

of Phase 1, the driver IC turns on the high-side MOSFET. The CS+

and CS– pins monitor the current through the sense resistor that

feeds both high-side MOSFETs. When the voltage between the

two pins exceeds the threshold level set by the voltage error ampli-

This signals the driver IC to turn off the high-side MOSFET and

turn on the low-side MOSFET. On the next cycle of the oscillator,

the driver logic toggles and sets PWM2 high. On each following

cycle of the oscillator, the outputs toggle between PWM1 and

PWM2. In each case, the current comparator resets the PWM

output low when the current comparator threshold is reached. As

the load current increases, the output voltage starts to decrease.

turn leads to an increase in the current comparator threshold,

thus programming more current to be delivered to the output so

that voltage regulation is maintained.

OUT

+

5V OR 12V

5V

5V

PWM1

PWM2

5V

OR

12V

ADP3160/

ADP3167

2-PHASE

SYNCHRONOUS

BUCK

CONTROLLER

ADP3412

SYNCHRONOUS

DRIVER

ADP3412

SYNCHRONOUS

DRIVER

PWM2

PWM1

Figure 5. 2-Phase CPU Supply System Level Block Diagram