LM9822 datasheet(20/22 Pages) NSC

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In this example, a 0.01µF capacitor takes 14 lines after power-up

to charge to its final value. On subsequent lines, the only error will

be the droop across a single line which should be significantly

less than the initial error. If the LM9822 is operating in CDS

mode and multiple lines are used to charge up the clamping

capacitors after power-up, then a clamp capacitor value of

0.01µF should be significantly greater than the calculated

CCLAMP MIN value and can virtually always be used.

If the LM9822 is operating in CIS mode, then significantly larger

clamp capacitors must be used. Fortunately, the output imped-

ance of most CIS sensors is significantly smaller than the output

impedance of CCD sensors, and R CLAMP will be dominated by

the 50

Ω from the LM9822 internal clamp switch. With a smaller

RCLAMP value, the clamp capacitors will charge faster.

7.0 Power Supply Considerations

The LM9822 analog supplies (

A) should be powered by a single

+5V source. The two analog supplies are brought out individually

to allow separate bypassing for each supply input. They should

not be powered by two or more different supplies.

Each supply input should be bypassed to its respective ground

with a 0.1µF capacitor located as close as possible to the supply

input pin. A single 10µF tantalum capacitor should be placed near

the VA supply pins to provide low frequency bypassing.

The V D input can be powered at 3.3Vor 5.0V. Power should be

supplied by a clean, low noise linear power supply, with a 0.1 µF

ceramic capacitor and a 10 µF tantalum capacitor placed near the

VD and DGND pins. If possible, a separate power and ground

plane should be provided to isolate the noisy digital output signals

from the sensitive analog supply pins. If the V D voltage is lower

than VA, a separate linear regulator should be used. If V D and A

are both at 5.0V, then they should be supplied by a common lin-

ear regulator, with separate analog and digital power and ground

planes.

To minimize noise, keep the LM9822 and all analog components

as far as possible from noise generators, such as switching power

supplies and high frequency digital busses. If possible, isolate all

the analog components and signals (OS, reference inputs and

outputs,

A, AGND) on an analog ground plane, separate from

the digital ground plane. The two ground planes should be tied

together at a single point, preferably the point where the power

supply enters the PCB.

8.0 Serial Interface and Configuration Registers

The serial interface is used to program the configuration registers

which control the operation of the LM9822. The SEN, SCLK, SDI

and SDO signals are used to set and verify configuration register

settings. In addition, MCLK must be active during all serial inter-

face activity. MCLK is used to register the level of the SEN input

and drives the logic that process information input on the SDI line.

9.0 Sample Mode Register Settings

A brief overview of the sample mode register and the bit locations

is give in Table 2: Configuration Register Parameters on page

14. The function of each bit is summarized in the following sec-

tions.

9.1 Output Driver Mode

The Output Driver Mode bit is normal set to 0. This bit can be set

to 1 to reduce the slew rate of the output drivers.

9.2 DOE (Data Output Edge) Setting

The Data Output Edge bit selects which edge of MCLK is used to

clock output data onto the output pins. For lowest noise perfor-

mance, this bit should be set to 0. With this setting, new data is

placed on the D7-D0 pins on every falling edge of MCLK. See

Diagrams 1 through 6 and Diagram 13 for more information on

data output timing for the different Divide By modes, and detailed

timing of the output data signals.

The bit can be set to 1 to adjust the data output timing for some

applications, but the noise performance of the LM9822 may be

somewhat degraded.

9.3 CDS Enable

The CDS Enable bit determines whether the sampling section of

the LM9822 operates in Correlated Double Sampling mode or in

Single Ended Sampling mode. CDS mode is normally used with

CCD type sensors, while Single Ended mode is normally used

with CIS type sensors.

9.4 Signal Polarity

Whether the LM9822 is operating in Correlated Double Sampling

Mode, or Single Ended Sampling mode, the basic sampling oper-

ation is the same. First a reference level is sampled, then a signal

level is sampled. For CDS mode operation, if the signal level is

lower in voltage than the reference level, the Signal Polarity bit

should be set to 0. This is the normal setting for CCD type sen-

sors. If the signal level is more positive than the reference level,

the Signal Polarity bit would be set to 1 for Positive Polarity mode.

When Single Ended Mode is selected, the Signal Polarity bit

determines which internal reference voltage is used to compare

with the input signal. Most CIS type sensors have a positive polar-

ity type output, and in this case the Signal Polarity Bit should be

set to 1. In this case, the internal VREF- is used as the reference

level during the Reference Sampling period.

In addition, the Signal Polarity bit determines which internal refer-

ence voltage is used during the Clamping interval. If Signal Polar-

ity = 0, V REF+ is used for clamping, if Signal Polarity = 1, V REF- is

used.

9.5 SMPCL

The SMPCL setting controls when the clamping action occurs

during the acquisition cycle. If SMPCL is set to 0, the Clamp will

be on for 1 MCLK before the reference sampling point. If SMPCL

is set to 1, clamping will occur in the interval after the reference

sampling point, and before the signal sampling point. In this case,

the clamping time is dependent on the present “Divide By” mode,

and the settings of the CDSREF bits.

9.6 CDSREF

The CDSREF setting is provided to allow adjustable sampling

points for the reference sample at the higher “Divide By” modes.

This may be useful to optimize the timing of the Reference Sam-

Applications Information (Continued)

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