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Diagram 4: Divide by 8 Monochrome Mode Sample and Data Output Timing (Green Input Shown)

VSMP

D7 -D0

Sample Signal

Sample Reference

MCLK

Level

Level

GH

GL

XX

XX

XX

XX

XX

XX

GH

GL

XX

H = d13-d6

L = d5-d0

ADC Clock

(internal)

N-1

N

N

N+1

N-4

N-3

XX

XX

DOE (Register 0, Bit 4) = 0

Diagram 5: Divide by 3 Monochrome Mode Sample and Data Output Timing (Green Input shown)

VSMP

D7 -D0

Sample Signal

Sample Reference

MCLK

Level

Level

GH

GL

GH

GL

GH

GL

GH

H = d13-d6

L = d5-d0

ADC Clock

(internal)

CDSREF = 00

N

N

N-1

N+1

N+1

N+2

N+2

N-11

N-10

N-9

GL

DOE (Register 0, Bit 4) = 0

Diagram 6: Divide by 2 Monochrome Mode Sample and Data Output Timing (Green Input shown)

VSMP

D7 -D0

Sample Signal

Sample Reference

MCLK

Level

Level

GH

GL

GL

GH

GH

GL

GH

GL

GH

GL

H = d13-d6

L = d5-d0

ADC Clock

(internal)

CDSREF = 00

N

N

N+1

N+1

N+2

N+2

N+3

N+3

N-1

N-1

N+4

N-11

N-10

N-9

N-8

N-7

DOE (Register 0, Bit 4) = 0