IR3093

Page 12 of 39

07/15/04

Figure 3 – 3 Phase Oscillator and PWM Waveforms

The RSFF is reset dominant allowing both phases to go to zero duty cycle within a few tens of nanoseconds in

response to a load step decrease. Phases can overlap and go to 100% duty cycle in response to a load step increase

with turn-on gated by the clock pulses. An Error Amplifier output voltage greater than the common mode input range of

the PWM comparator results in 100% duty cycle regardless of the voltage of the PWM ramp. This arrangement

guarantees the Error Amplifier is always in control and can demand 0 to 100% duty cycle as required. It also favors

response to a load step decrease which is appropriate given the low output to input voltage ratio of most systems. The

inductor current will increase much more rapidly than decrease in response to load transients.

This control method is designed to provide “single cycle transient response” where the inductor current changes in

response to load transients within a single switching cycle maximizing the effectiveness of the power train and

minimizing the output capacitor requirements.

In a conventional synchronous buck converter, the minimum time required to reduce the current in the inductor in

response to a load step decrease is;

The slew rate of the inductor current can be significantly increased by turning off the synchronous rectifier in response

to a load step decrease. The switch node voltage is then forced to decrease until conduction of the synchronous

minimum time required to reduce the current in the inductor in response to a load transient decrease is now;

CLK1

CLK3

50% INTERNAL OSCILLATOR RAMP

DUTY CYCLE

RAMP1 SLOPE = 50mV / % DC

0.6V

FIXED RAMP1

EAOUT

RAMP3

RAMP3 MIN DUTY

CYCLE ADJUST

RAMP3 MAX DUTY

CYCLE ADJUST

THE SHARE ADJUST ERROR AMPLIFIER CAN

CHANGE THE PULSE WIDTH OF RAMPS 2 & 3 FROM

0.5 x RAMP1 TO 2.0 X RAMP1 TO FORCE

CURRENT SHARING.

CLK2

RAMP2