X9521 datasheet(12/26 Pages) XICOR

12 / 26 page

REV 1.1.9 1/30/03

Characteristics subject to change without notice.

12 of 26

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X9521

– Preliminary Information

ter now responds with an ACKNOWLEDGE, indicating it

requires additional data. The X9521 continues to output a

Data Byte for each ACKNOWLEDGE received. The mas-

ter terminates the read operation by not responding with

an ACKNOWLEDGE and instead issuing a STOP condi-

tion.

The data output is sequential, with the data from address

n followed by the data from address n + 1. The address

counter for read operations increments through the entire

memory contents to be serially read during one operation.

At the end of the address space the counter “rolls over” to

address 00h and the device continues to output data for

each ACKNOWLEDGE received (Refer to Figure 16.).

CONTROL AND STATUS REGISTER

The Control and Status (CONSTAT) Register provides the

user with a mechanism for changing and reading the sta-

tus of various parameters of the X9521 (See Figure 17).

The CONSTAT register is a combination of both volatile

and nonvolatile bits. The nonvolatile bits of the CONSTAT

ered down, then powered back up. The volatile bits how-

ever, will always power up to a known logic state “0”

(irrespective of their value at power down).

A detailed description of the function of each of the CON-

STAT register bits follows:

WEL: Write Enable Latch (Volatile)

The WEL bit controls the Write Enable status of the entire

X9521 device. This bit must ﬁrst be enabled before ANY

write operation (to DCPs, EEPROM memory array, or the

CONSTAT register). If the WEL bit is not ﬁrst enabled,

then ANY proceeding (volatile or nonvolatile) write opera-

tion to DCPs, EEPROM array, as well as the CONSTAT

after a Data Byte.

The WEL bit is a volatile latch that powers up in the dis-

abled, LOW (0) state. The WEL bit is enabled / set by writ-

ing 00000010 to the CONSTAT register. Once enabled,

the WEL bit remains set to “1” until either it is reset to “0”

(by writing 00000000 to the CONSTAT register) or until

the X9521 powers down, and then up again.

Writes to the WEL bit do not cause an internal high volt-

age write cycle. Therefore, the device is ready for another

operation immediately after a STOP condition is executed

in the CONSTAT Write command sequence (See Figure

18).

RWEL: Register Write Enable Latch (Volatile)

The RWEL bit controls the (CONSTAT) Register Write

Enable status of the X9521. Therefore, in order to write to

any of the bits of the CONSTAT Register (except WEL),

the RWEL bit must ﬁrst be set to “1”. The RWEL bit is a

volatile bit that powers up in the disabled, LOW (“0”) state.

It must be noted that the RWEL bit can only be set, once

the WEL bit has ﬁrst been enabled (See "CONSTAT Reg-

ister Write Operation").

The RWEL bit will reset itself to the default “0” state, in

one of three cases:

—After a successful write operation to any bits of the

CONSTAT register has been completed (See Figure

18).

—When the X9521 is powered down.

—When attempting to write to a Block Lock protected

region of the EEPROM memory (See "BL1, BL0: Block

Lock protection bits - (Nonvolatile)", below).

BL1, BL0: Block Lock protection bits - (Nonvolatile)

The Block Lock protection bits (BL1 and BL0) are used to:

—Inhibit a write operation from being performed to certain

addresses of the EEPROM memory array

—Inhibit a DCP write operation (changing the “wiper posi-

tion”).

Bit(s)

Description

CS7 - CS5

Always “0”(RESERVED)

BL1 - BL0

Sets the Block Lock partition

RWEL

WEL

Write Enable Latch bit

CS0

Always “0” (RESERVED)

WEL

CS5

CS6

CS7

CS4

CS3

CS2

CS1

CS0

BL0

BL1

RWEL

Figure 17. CONSTAT Register Format

NOTE: Bits labelled NV are nonvolatile (See “CONTROL AND STATUS REGISTER”).

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